/*
 * Copyright (c) [2020], MediaTek Inc. All rights reserved.
 *
 * This software/firmware and related documentation ("MediaTek Software") are
 * protected under relevant copyright laws.
 * The information contained herein is confidential and proprietary to
 * MediaTek Inc. and/or its licensors.
 * Except as otherwise provided in the applicable licensing terms with
 * MediaTek Inc. and/or its licensors, any reproduction, modification, use or
 * disclosure of MediaTek Software, and information contained herein, in whole
 * or in part, shall be strictly prohibited.
*/
//[File]            : wf_m2m_phy_top_11ax.h
//[Revision time]   : Thu Aug 16 16:54:35 2018
//[Description]     : This file is auto generated by CODA
//[Copyright]       : Copyright (C) 2018 Mediatek Incorportion. All rights reserved.

#ifndef __WF_M2M_PHY_TOP_11AX_REGS_H__
#define __WF_M2M_PHY_TOP_11AX_REGS_H__

#include "hal_common.h"

#ifdef __cplusplus
extern "C" {
#endif


//****************************************************************************
//
//                     WF_M2M_PHY_TOP_11AX CR Definitions
//
//****************************************************************************

#define WF_M2M_PHY_TOP_11AX_BASE                               0x83000000

#define WF_M2M_PHY_TOP_11AX_M2M_U0_CCAPER0_ADDR                (WF_M2M_PHY_TOP_11AX_BASE + 0x58) // 0058
#define WF_M2M_PHY_TOP_11AX_M2M_U0_PER1_ADDR                   (WF_M2M_PHY_TOP_11AX_BASE + 0x88) // 0088
#define WF_M2M_PHY_TOP_11AX_M2M_U0_PER2_ADDR                   (WF_M2M_PHY_TOP_11AX_BASE + 0x8c) // 008C
#define WF_M2M_PHY_TOP_11AX_M2M_U0_PER3_ADDR                   (WF_M2M_PHY_TOP_11AX_BASE + 0x90) // 0090
#define WF_M2M_PHY_TOP_11AX_M2M_U0_PER4_ADDR                   (WF_M2M_PHY_TOP_11AX_BASE + 0x94) // 0094
#define WF_M2M_PHY_TOP_11AX_M2M_U0_PER5_ADDR                   (WF_M2M_PHY_TOP_11AX_BASE + 0x98) // 0098
#define WF_M2M_PHY_TOP_11AX_M2M_U0_PER6_ADDR                   (WF_M2M_PHY_TOP_11AX_BASE + 0x9c) // 009C
#define WF_M2M_PHY_TOP_11AX_M2M_U0_PER7_ADDR                   (WF_M2M_PHY_TOP_11AX_BASE + 0xA0) // 00A0
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC1_ADDR                    (WF_M2M_PHY_TOP_11AX_BASE + 0x210) // 0210
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC2_ADDR                    (WF_M2M_PHY_TOP_11AX_BASE + 0x214) // 0214
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC3_ADDR                    (WF_M2M_PHY_TOP_11AX_BASE + 0x218) // 0218
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC4_ADDR                    (WF_M2M_PHY_TOP_11AX_BASE + 0x21c) // 021C
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC5_ADDR                    (WF_M2M_PHY_TOP_11AX_BASE + 0x220) // 0220
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC6_ADDR                    (WF_M2M_PHY_TOP_11AX_BASE + 0x224) // 0224
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC7_ADDR                    (WF_M2M_PHY_TOP_11AX_BASE + 0x228) // 0228
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC8_ADDR                    (WF_M2M_PHY_TOP_11AX_BASE + 0x22c) // 022C
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC9_ADDR                    (WF_M2M_PHY_TOP_11AX_BASE + 0x230) // 0230
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC10_ADDR                   (WF_M2M_PHY_TOP_11AX_BASE + 0x234) // 0234
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC11_ADDR                   (WF_M2M_PHY_TOP_11AX_BASE + 0x238) // 0238
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC12_ADDR                   (WF_M2M_PHY_TOP_11AX_BASE + 0x23c) // 023C
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC13_ADDR                   (WF_M2M_PHY_TOP_11AX_BASE + 0x240) // 0240
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC14_ADDR                   (WF_M2M_PHY_TOP_11AX_BASE + 0x244) // 0244
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC15_ADDR                   (WF_M2M_PHY_TOP_11AX_BASE + 0x248) // 0248
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC16_ADDR                   (WF_M2M_PHY_TOP_11AX_BASE + 0x24c) // 024C
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC17_ADDR                   (WF_M2M_PHY_TOP_11AX_BASE + 0x250) // 0250
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC18_ADDR                   (WF_M2M_PHY_TOP_11AX_BASE + 0x254) // 0254
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC19_ADDR                   (WF_M2M_PHY_TOP_11AX_BASE + 0x258) // 0258
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC20_ADDR                   (WF_M2M_PHY_TOP_11AX_BASE + 0x25c) // 025C
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC21_ADDR                   (WF_M2M_PHY_TOP_11AX_BASE + 0x260) // 0260
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC22_ADDR                   (WF_M2M_PHY_TOP_11AX_BASE + 0x264) // 0264
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC23_ADDR                   (WF_M2M_PHY_TOP_11AX_BASE + 0x268) // 0268
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC24_ADDR                   (WF_M2M_PHY_TOP_11AX_BASE + 0x26c) // 026C
#define WF_M2M_PHY_TOP_11AX_M2M_FALSE_CCAPRI_ADDR              (WF_M2M_PHY_TOP_11AX_BASE + 0x454) // 0454
#define WF_M2M_PHY_TOP_11AX_M2M_FALSE_CCA20_ADDR               (WF_M2M_PHY_TOP_11AX_BASE + 0x458) // 0458
#define WF_M2M_PHY_TOP_11AX_M2M_FALSE_CCA40_ADDR               (WF_M2M_PHY_TOP_11AX_BASE + 0x45c) // 045C
#define WF_M2M_PHY_TOP_11AX_M2M_FALSE_CCA80_ADDR               (WF_M2M_PHY_TOP_11AX_BASE + 0x460) // 0460
#define WF_M2M_PHY_TOP_11AX_M2M_TXV1_ADDR                      (WF_M2M_PHY_TOP_11AX_BASE + 0x630) // 0630
#define WF_M2M_PHY_TOP_11AX_M2M_TXV2_ADDR                      (WF_M2M_PHY_TOP_11AX_BASE + 0x634) // 0634
#define WF_M2M_PHY_TOP_11AX_M2M_TXV3_ADDR                      (WF_M2M_PHY_TOP_11AX_BASE + 0x638) // 0638
#define WF_M2M_PHY_TOP_11AX_M2M_TXV4_ADDR                      (WF_M2M_PHY_TOP_11AX_BASE + 0x63c) // 063C
#define WF_M2M_PHY_TOP_11AX_M2M_TXV5_ADDR                      (WF_M2M_PHY_TOP_11AX_BASE + 0x640) // 0640
#define WF_M2M_PHY_TOP_11AX_M2M_TXV6_ADDR                      (WF_M2M_PHY_TOP_11AX_BASE + 0x644) // 0644
#define WF_M2M_PHY_TOP_11AX_M2M_TXV7_ADDR                      (WF_M2M_PHY_TOP_11AX_BASE + 0x648) // 0648
#define WF_M2M_PHY_TOP_11AX_M2M_TXV8_ADDR                      (WF_M2M_PHY_TOP_11AX_BASE + 0x64c) // 064C
#define WF_M2M_PHY_TOP_11AX_M2M_TXV9_ADDR                      (WF_M2M_PHY_TOP_11AX_BASE + 0x650) // 0650
#define WF_M2M_PHY_TOP_11AX_M2M_TXV10_ADDR                     (WF_M2M_PHY_TOP_11AX_BASE + 0x654) // 0654
#define WF_M2M_PHY_TOP_11AX_M2M_TXV11_ADDR                     (WF_M2M_PHY_TOP_11AX_BASE + 0x658) // 0658
#define WF_M2M_PHY_TOP_11AX_M2M_TXV12_ADDR                     (WF_M2M_PHY_TOP_11AX_BASE + 0x65c) // 065C
#define WF_M2M_PHY_TOP_11AX_M2M_TXV13_ADDR                     (WF_M2M_PHY_TOP_11AX_BASE + 0x660) // 0660
#define WF_M2M_PHY_TOP_11AX_M2M_TXV14_ADDR                     (WF_M2M_PHY_TOP_11AX_BASE + 0x664) // 0664
#define WF_M2M_PHY_TOP_11AX_M2M_TXV15_ADDR                     (WF_M2M_PHY_TOP_11AX_BASE + 0x668) // 0668
#define WF_M2M_PHY_TOP_11AX_M2M_TXV16_ADDR                     (WF_M2M_PHY_TOP_11AX_BASE + 0x66c) // 066C
#define WF_M2M_PHY_TOP_11AX_M2M_TXV17_ADDR                     (WF_M2M_PHY_TOP_11AX_BASE + 0x670) // 0670
#define WF_M2M_PHY_TOP_11AX_M2M_TXV18_ADDR                     (WF_M2M_PHY_TOP_11AX_BASE + 0x674) // 0674
#define WF_M2M_PHY_TOP_11AX_M2M_TXV19_ADDR                     (WF_M2M_PHY_TOP_11AX_BASE + 0x678) // 0678
#define WF_M2M_PHY_TOP_11AX_M2M_TXV20_ADDR                     (WF_M2M_PHY_TOP_11AX_BASE + 0x67c) // 067C
#define WF_M2M_PHY_TOP_11AX_M2M_TXV21_ADDR                     (WF_M2M_PHY_TOP_11AX_BASE + 0x680) // 0680
#define WF_M2M_PHY_TOP_11AX_M2M_TXV22_ADDR                     (WF_M2M_PHY_TOP_11AX_BASE + 0x684) // 0684
#define WF_M2M_PHY_TOP_11AX_M2M_TXV23_ADDR                     (WF_M2M_PHY_TOP_11AX_BASE + 0x688) // 0688
#define WF_M2M_PHY_TOP_11AX_M2M_TXV24_ADDR                     (WF_M2M_PHY_TOP_11AX_BASE + 0x68c) // 068C
#define WF_M2M_PHY_TOP_11AX_M2M_TPC_ADDR                       (WF_M2M_PHY_TOP_11AX_BASE + 0xC08) // 0C08
#define WF_M2M_PHY_TOP_11AX_M2M_PER_BYTECNT_ADDR               (WF_M2M_PHY_TOP_11AX_BASE + 0xC64) // 0C64
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_CTRL_ADDR                (WF_M2M_PHY_TOP_11AX_BASE + 0x1000) // 1000
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_UID_DATA_ADDR            (WF_M2M_PHY_TOP_11AX_BASE + 0x1004) // 1004
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_UID_STATUS_ADDR          (WF_M2M_PHY_TOP_11AX_BASE + 0x1008) // 1008
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_PPDU_DATA_ADDR           (WF_M2M_PHY_TOP_11AX_BASE + 0x100C) // 100C
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_PPDU_STATUS_ADDR         (WF_M2M_PHY_TOP_11AX_BASE + 0x1010) // 1010
#define WF_M2M_PHY_TOP_11AX_M2M_TXVEC_EXT1_U0_ADDR             (WF_M2M_PHY_TOP_11AX_BASE + 0x1040) // 1040
#define WF_M2M_PHY_TOP_11AX_M2M_TXVEC_EXT2_U0_ADDR             (WF_M2M_PHY_TOP_11AX_BASE + 0x1044) // 1044
#define WF_M2M_PHY_TOP_11AX_M2M_TXVEC_EXT3_U0_ADDR             (WF_M2M_PHY_TOP_11AX_BASE + 0x1048) // 1048
#define WF_M2M_PHY_TOP_11AX_M2M_TXVEC_EXT1_U1_ADDR             (WF_M2M_PHY_TOP_11AX_BASE + 0x104c) // 104C
#define WF_M2M_PHY_TOP_11AX_M2M_TXVEC_EXT2_U1_ADDR             (WF_M2M_PHY_TOP_11AX_BASE + 0x1050) // 1050
#define WF_M2M_PHY_TOP_11AX_M2M_TXVEC_EXT3_U1_ADDR             (WF_M2M_PHY_TOP_11AX_BASE + 0x1054) // 1054
#define WF_M2M_PHY_TOP_11AX_M2M_TXVEC_EXT1_U2_ADDR             (WF_M2M_PHY_TOP_11AX_BASE + 0x1058) // 1058
#define WF_M2M_PHY_TOP_11AX_M2M_TXVEC_EXT2_U2_ADDR             (WF_M2M_PHY_TOP_11AX_BASE + 0x105c) // 105C
#define WF_M2M_PHY_TOP_11AX_M2M_TXVEC_EXT3_U2_ADDR             (WF_M2M_PHY_TOP_11AX_BASE + 0x1060) // 1060
#define WF_M2M_PHY_TOP_11AX_M2M_TXVEC_EXT1_U3_ADDR             (WF_M2M_PHY_TOP_11AX_BASE + 0x1064) // 1064
#define WF_M2M_PHY_TOP_11AX_M2M_TXVEC_EXT2_U3_ADDR             (WF_M2M_PHY_TOP_11AX_BASE + 0x1068) // 1068
#define WF_M2M_PHY_TOP_11AX_M2M_TXVEC_EXT3_U3_ADDR             (WF_M2M_PHY_TOP_11AX_BASE + 0x106c) // 106C
#define WF_M2M_PHY_TOP_11AX_M2M_TX_MANUAL_MODE_ADDR            (WF_M2M_PHY_TOP_11AX_BASE + 0x1100) // 1100
#define WF_M2M_PHY_TOP_11AX_M2M_U0_TX_DATA_ADDR                (WF_M2M_PHY_TOP_11AX_BASE + 0x1110) // 1110
#define WF_M2M_PHY_TOP_11AX_M2M_U1_TX_DATA_ADDR                (WF_M2M_PHY_TOP_11AX_BASE + 0x1114) // 1114
#define WF_M2M_PHY_TOP_11AX_M2M_U2_TX_DATA_ADDR                (WF_M2M_PHY_TOP_11AX_BASE + 0x1118) // 1118
#define WF_M2M_PHY_TOP_11AX_M2M_U3_TX_DATA_ADDR                (WF_M2M_PHY_TOP_11AX_BASE + 0x111c) // 111C
#define WF_M2M_PHY_TOP_11AX_M2M_U0_RX_DATA_ADDR                (WF_M2M_PHY_TOP_11AX_BASE + 0x1150) // 1150
#define WF_M2M_PHY_TOP_11AX_M2M_U1_RX_DATA_ADDR                (WF_M2M_PHY_TOP_11AX_BASE + 0x1154) // 1154
#define WF_M2M_PHY_TOP_11AX_M2M_U2_RX_DATA_ADDR                (WF_M2M_PHY_TOP_11AX_BASE + 0x1158) // 1158
#define WF_M2M_PHY_TOP_11AX_M2M_U3_RX_DATA_ADDR                (WF_M2M_PHY_TOP_11AX_BASE + 0x115c) // 115C
#define WF_M2M_PHY_TOP_11AX_M2M_STAID_0_ADDR                   (WF_M2M_PHY_TOP_11AX_BASE + 0x1200) // 1200
#define WF_M2M_PHY_TOP_11AX_M2M_STAID_1_ADDR                   (WF_M2M_PHY_TOP_11AX_BASE + 0x1204) // 1204
#define WF_M2M_PHY_TOP_11AX_M2M_LENGTH_CHK0_ADDR               (WF_M2M_PHY_TOP_11AX_BASE + 0x1300) // 1300
#define WF_M2M_PHY_TOP_11AX_M2M_LENGTH_CHK1_ADDR               (WF_M2M_PHY_TOP_11AX_BASE + 0x1304) // 1304
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC_EXT1_U0_ADDR             (WF_M2M_PHY_TOP_11AX_BASE + 0x2010) // 2010
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC_EXT2_U0_ADDR             (WF_M2M_PHY_TOP_11AX_BASE + 0x2014) // 2014
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC_EXT3_U0_ADDR             (WF_M2M_PHY_TOP_11AX_BASE + 0x2018) // 2018
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC_EXT1_U1_ADDR             (WF_M2M_PHY_TOP_11AX_BASE + 0x201c) // 201C
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC_EXT2_U1_ADDR             (WF_M2M_PHY_TOP_11AX_BASE + 0x2020) // 2020
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC_EXT3_U1_ADDR             (WF_M2M_PHY_TOP_11AX_BASE + 0x2024) // 2024
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC_EXT1_U2_ADDR             (WF_M2M_PHY_TOP_11AX_BASE + 0x2028) // 2028
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC_EXT2_U2_ADDR             (WF_M2M_PHY_TOP_11AX_BASE + 0x202c) // 202C
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC_EXT3_U2_ADDR             (WF_M2M_PHY_TOP_11AX_BASE + 0x2030) // 2030
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC_EXT1_U3_ADDR             (WF_M2M_PHY_TOP_11AX_BASE + 0x2034) // 2034
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC_EXT2_U3_ADDR             (WF_M2M_PHY_TOP_11AX_BASE + 0x2038) // 2038
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC_EXT3_U3_ADDR             (WF_M2M_PHY_TOP_11AX_BASE + 0x203c) // 203C
#define WF_M2M_PHY_TOP_11AX_M2M_RX_CTRL_ADDR                   (WF_M2M_PHY_TOP_11AX_BASE + 0x2100) // 2100
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CB0_DW0_ADDR               (WF_M2M_PHY_TOP_11AX_BASE + 0x2110) // 2110
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CB1_DW0_ADDR               (WF_M2M_PHY_TOP_11AX_BASE + 0x2118) // 2118
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CB2_DW0_ADDR               (WF_M2M_PHY_TOP_11AX_BASE + 0x2120) // 2120
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CB2_DW1_ADDR               (WF_M2M_PHY_TOP_11AX_BASE + 0x2124) // 2124
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CB3_DW0_ADDR               (WF_M2M_PHY_TOP_11AX_BASE + 0x2128) // 2128
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CB3_DW1_ADDR               (WF_M2M_PHY_TOP_11AX_BASE + 0x212C) // 212C
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CB4_DW0_ADDR               (WF_M2M_PHY_TOP_11AX_BASE + 0x2130) // 2130
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CB4_DW1_ADDR               (WF_M2M_PHY_TOP_11AX_BASE + 0x2134) // 2134
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CB5_DW0_ADDR               (WF_M2M_PHY_TOP_11AX_BASE + 0x2138) // 2138
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CB5_DW1_ADDR               (WF_M2M_PHY_TOP_11AX_BASE + 0x213C) // 213C
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CB6_DW0_ADDR               (WF_M2M_PHY_TOP_11AX_BASE + 0x2140) // 2140
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CB6_DW1_ADDR               (WF_M2M_PHY_TOP_11AX_BASE + 0x2144) // 2144
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CB7_DW0_ADDR               (WF_M2M_PHY_TOP_11AX_BASE + 0x2148) // 2148
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CB7_DW1_ADDR               (WF_M2M_PHY_TOP_11AX_BASE + 0x214C) // 214C
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CB8_DW0_ADDR               (WF_M2M_PHY_TOP_11AX_BASE + 0x2150) // 2150
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CB8_DW1_ADDR               (WF_M2M_PHY_TOP_11AX_BASE + 0x2154) // 2154
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_PB0_DW0_ADDR               (WF_M2M_PHY_TOP_11AX_BASE + 0x2200) // 2200
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_PB0_DW1_ADDR               (WF_M2M_PHY_TOP_11AX_BASE + 0x2204) // 2204
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_PA0_DW0_ADDR               (WF_M2M_PHY_TOP_11AX_BASE + 0x2280) // 2280
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_PA0_DW1_ADDR               (WF_M2M_PHY_TOP_11AX_BASE + 0x2284) // 2284
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_PA1_DW0_ADDR               (WF_M2M_PHY_TOP_11AX_BASE + 0x2288) // 2288
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_PA1_DW1_ADDR               (WF_M2M_PHY_TOP_11AX_BASE + 0x228C) // 228C
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_PA2_DW0_ADDR               (WF_M2M_PHY_TOP_11AX_BASE + 0x2290) // 2290
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_PA2_DW1_ADDR               (WF_M2M_PHY_TOP_11AX_BASE + 0x2294) // 2294
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA0_DW0_ADDR               (WF_M2M_PHY_TOP_11AX_BASE + 0x2300) // 2300
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA0_DW1_ADDR               (WF_M2M_PHY_TOP_11AX_BASE + 0x2304) // 2304
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA1_DW0_ADDR               (WF_M2M_PHY_TOP_11AX_BASE + 0x2308) // 2308
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA1_DW1_ADDR               (WF_M2M_PHY_TOP_11AX_BASE + 0x230C) // 230C
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA2_DW0_ADDR               (WF_M2M_PHY_TOP_11AX_BASE + 0x2310) // 2310
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA2_DW1_ADDR               (WF_M2M_PHY_TOP_11AX_BASE + 0x2314) // 2314
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA3_DW0_ADDR               (WF_M2M_PHY_TOP_11AX_BASE + 0x2318) // 2318
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA3_DW1_ADDR               (WF_M2M_PHY_TOP_11AX_BASE + 0x231C) // 231C
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA4_DW0_ADDR               (WF_M2M_PHY_TOP_11AX_BASE + 0x2320) // 2320
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA4_DW1_ADDR               (WF_M2M_PHY_TOP_11AX_BASE + 0x2324) // 2324
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA5_DW0_ADDR               (WF_M2M_PHY_TOP_11AX_BASE + 0x2328) // 2328
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA5_DW1_ADDR               (WF_M2M_PHY_TOP_11AX_BASE + 0x232C) // 232C
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA6_DW0_ADDR               (WF_M2M_PHY_TOP_11AX_BASE + 0x2330) // 2330
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA6_DW1_ADDR               (WF_M2M_PHY_TOP_11AX_BASE + 0x2334) // 2334
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA7_DW0_ADDR               (WF_M2M_PHY_TOP_11AX_BASE + 0x2338) // 2338
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA7_DW1_ADDR               (WF_M2M_PHY_TOP_11AX_BASE + 0x233C) // 233C
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA8_DW0_ADDR               (WF_M2M_PHY_TOP_11AX_BASE + 0x2340) // 2340
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA8_DW1_ADDR               (WF_M2M_PHY_TOP_11AX_BASE + 0x2344) // 2344
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA9_DW0_ADDR               (WF_M2M_PHY_TOP_11AX_BASE + 0x2348) // 2348
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA9_DW1_ADDR               (WF_M2M_PHY_TOP_11AX_BASE + 0x234C) // 234C
#define WF_M2M_PHY_TOP_11AX_M2M_RX_TRIG_CFG_DW0_ADDR           (WF_M2M_PHY_TOP_11AX_BASE + 0x2500) // 2500
#define WF_M2M_PHY_TOP_11AX_M2M_RX_TRIG_CFG_DW1_ADDR           (WF_M2M_PHY_TOP_11AX_BASE + 0x2504) // 2504
#define WF_M2M_PHY_TOP_11AX_M2M_RX_TRIG_COM_DW0_ADDR           (WF_M2M_PHY_TOP_11AX_BASE + 0x2508) // 2508
#define WF_M2M_PHY_TOP_11AX_M2M_RX_TRIG_COM_DW1_ADDR           (WF_M2M_PHY_TOP_11AX_BASE + 0x250C) // 250C
#define WF_M2M_PHY_TOP_11AX_M2M_RX_TRIG_DDW0_DW0_ADDR          (WF_M2M_PHY_TOP_11AX_BASE + 0x2510) // 2510
#define WF_M2M_PHY_TOP_11AX_M2M_RX_TRIG_DDW0_DW1_ADDR          (WF_M2M_PHY_TOP_11AX_BASE + 0x2514) // 2514
#define WF_M2M_PHY_TOP_11AX_M2M_RX_TRIG_DDW1_DW0_ADDR          (WF_M2M_PHY_TOP_11AX_BASE + 0x2518) // 2518
#define WF_M2M_PHY_TOP_11AX_M2M_RX_TRIG_DDW1_DW1_ADDR          (WF_M2M_PHY_TOP_11AX_BASE + 0x251C) // 251C
#define WF_M2M_PHY_TOP_11AX_M2M_MAC_PHY_INTF_CTRL_ADDR         (WF_M2M_PHY_TOP_11AX_BASE + 0x3000) // 3000
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_CTRL_ADDR                  (WF_M2M_PHY_TOP_11AX_BASE + 0x3010) // 3010
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_BER_ADDR                   (WF_M2M_PHY_TOP_11AX_BASE + 0x3014) // 3014
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_TICK_CTRL_0_ADDR           (WF_M2M_PHY_TOP_11AX_BASE + 0x3018) // 3018
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_TICK_CTRL_1_ADDR           (WF_M2M_PHY_TOP_11AX_BASE + 0x301C) // 301C
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U0_TX_ERR_ADDR             (WF_M2M_PHY_TOP_11AX_BASE + 0x3020) // 3020
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U1_TX_ERR_ADDR             (WF_M2M_PHY_TOP_11AX_BASE + 0x3024) // 3024
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U2_TX_ERR_ADDR             (WF_M2M_PHY_TOP_11AX_BASE + 0x3028) // 3028
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U3_TX_ERR_ADDR             (WF_M2M_PHY_TOP_11AX_BASE + 0x302c) // 302C
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U0_RX_ERR_ADDR             (WF_M2M_PHY_TOP_11AX_BASE + 0x3040) // 3040
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U1_RX_ERR_ADDR             (WF_M2M_PHY_TOP_11AX_BASE + 0x3044) // 3044
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U2_RX_ERR_ADDR             (WF_M2M_PHY_TOP_11AX_BASE + 0x3048) // 3048
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U3_RX_ERR_ADDR             (WF_M2M_PHY_TOP_11AX_BASE + 0x304c) // 304C
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U0_BER_VALUE_ADDR          (WF_M2M_PHY_TOP_11AX_BASE + 0x3060) // 3060
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U0_TX_BER_0_ADDR           (WF_M2M_PHY_TOP_11AX_BASE + 0x3080) // 3080
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U0_TX_BER_1_ADDR           (WF_M2M_PHY_TOP_11AX_BASE + 0x3084) // 3084
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U0_RX_BER_0_ADDR           (WF_M2M_PHY_TOP_11AX_BASE + 0x30a0) // 30A0
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U0_RX_BER_1_ADDR           (WF_M2M_PHY_TOP_11AX_BASE + 0x30a4) // 30A4




/* =====================================================================================

  ---M2M_U0_CCAPER0 (0x83000000 + 0x58)---

    CCK_PER1[15..0]              - (RW) CCK: PER per rate
                                     [3:0] 1M,
                                     [7:4] 2M,
                                     [11:8] 5.5M,
                                     [15:12] 11M
                                     4'h0 : Random 0% PER
                                     4'h1 : Random 5% PER
                                     4'h2 : Random 10% PER
                                     4'h3 : Random 15% PER
                                     4'h4 : Random 20% PER
                                     4'h5 : Random 25% PER
                                     4'h6 : Random 30% PER
                                     4'h7 : Random 35% PER
                                     4'h8 : Random 40% PER
                                     4'h9 : Random 45% PER
                                     4'hA : Random 50% PER
                                     4'hB : Random 55% PER
                                     4'hC : Random 60% PER
                                     4'hD : Random 70% PER
                                     4'hE : Random 80% PER
                                     4'hF : Random 90% PER
    NOISY_EN[16]                 - (RW) 0: Disable False Primary CCA, 1: Enable Fasle Primary CCA
    NOISY_MODE[17]               - (RW) 0: False Primary CCA Light Mode, 1: Fasle Primary CCA Normal Mode
    SEC20_NOISY_EN[18]           - (RW) 0: Disable False SEC20 CCA, 1: Enable Fasle SEC20 CCA
    SEC20_NOISY_MODE[19]         - (RW) 0: False SEC20 CCA Light Mode, 1: Fasle SEC20 CCA Normal Mode
    SEC40_NOISY_EN[20]           - (RW) 0: Disable False SEC40 CCA, 1: Enable Fasle SEC40 CCA
    SEC40_NOISY_MODE[21]         - (RW) 0: False SEC40 CCA Light Mode, 1: Fasle SEC40 CCA Normal Mode
    SEC80_NOISY_EN[22]           - (RW) 0: Disable False SEC80 CCA, 1: Enable Fasle SEC80 CCA
    SEC80_NOISY_MODE[23]         - (RW) 0: False SEC80 CCA Light Mode, 1: Fasle SEC80 CCA Normal Mode
    RESERVED24[31..24]           - (RO) Reserved bits

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_U0_CCAPER0_SEC80_NOISY_MODE_ADDR WF_M2M_PHY_TOP_11AX_M2M_U0_CCAPER0_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_U0_CCAPER0_SEC80_NOISY_MODE_MASK 0x00800000                // SEC80_NOISY_MODE[23]
#define WF_M2M_PHY_TOP_11AX_M2M_U0_CCAPER0_SEC80_NOISY_MODE_SHFT 23
#define WF_M2M_PHY_TOP_11AX_M2M_U0_CCAPER0_SEC80_NOISY_EN_ADDR WF_M2M_PHY_TOP_11AX_M2M_U0_CCAPER0_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_U0_CCAPER0_SEC80_NOISY_EN_MASK 0x00400000                // SEC80_NOISY_EN[22]
#define WF_M2M_PHY_TOP_11AX_M2M_U0_CCAPER0_SEC80_NOISY_EN_SHFT 22
#define WF_M2M_PHY_TOP_11AX_M2M_U0_CCAPER0_SEC40_NOISY_MODE_ADDR WF_M2M_PHY_TOP_11AX_M2M_U0_CCAPER0_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_U0_CCAPER0_SEC40_NOISY_MODE_MASK 0x00200000                // SEC40_NOISY_MODE[21]
#define WF_M2M_PHY_TOP_11AX_M2M_U0_CCAPER0_SEC40_NOISY_MODE_SHFT 21
#define WF_M2M_PHY_TOP_11AX_M2M_U0_CCAPER0_SEC40_NOISY_EN_ADDR WF_M2M_PHY_TOP_11AX_M2M_U0_CCAPER0_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_U0_CCAPER0_SEC40_NOISY_EN_MASK 0x00100000                // SEC40_NOISY_EN[20]
#define WF_M2M_PHY_TOP_11AX_M2M_U0_CCAPER0_SEC40_NOISY_EN_SHFT 20
#define WF_M2M_PHY_TOP_11AX_M2M_U0_CCAPER0_SEC20_NOISY_MODE_ADDR WF_M2M_PHY_TOP_11AX_M2M_U0_CCAPER0_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_U0_CCAPER0_SEC20_NOISY_MODE_MASK 0x00080000                // SEC20_NOISY_MODE[19]
#define WF_M2M_PHY_TOP_11AX_M2M_U0_CCAPER0_SEC20_NOISY_MODE_SHFT 19
#define WF_M2M_PHY_TOP_11AX_M2M_U0_CCAPER0_SEC20_NOISY_EN_ADDR WF_M2M_PHY_TOP_11AX_M2M_U0_CCAPER0_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_U0_CCAPER0_SEC20_NOISY_EN_MASK 0x00040000                // SEC20_NOISY_EN[18]
#define WF_M2M_PHY_TOP_11AX_M2M_U0_CCAPER0_SEC20_NOISY_EN_SHFT 18
#define WF_M2M_PHY_TOP_11AX_M2M_U0_CCAPER0_NOISY_MODE_ADDR     WF_M2M_PHY_TOP_11AX_M2M_U0_CCAPER0_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_U0_CCAPER0_NOISY_MODE_MASK     0x00020000                // NOISY_MODE[17]
#define WF_M2M_PHY_TOP_11AX_M2M_U0_CCAPER0_NOISY_MODE_SHFT     17
#define WF_M2M_PHY_TOP_11AX_M2M_U0_CCAPER0_NOISY_EN_ADDR       WF_M2M_PHY_TOP_11AX_M2M_U0_CCAPER0_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_U0_CCAPER0_NOISY_EN_MASK       0x00010000                // NOISY_EN[16]
#define WF_M2M_PHY_TOP_11AX_M2M_U0_CCAPER0_NOISY_EN_SHFT       16
#define WF_M2M_PHY_TOP_11AX_M2M_U0_CCAPER0_CCK_PER1_ADDR       WF_M2M_PHY_TOP_11AX_M2M_U0_CCAPER0_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_U0_CCAPER0_CCK_PER1_MASK       0x0000FFFF                // CCK_PER1[15..0]
#define WF_M2M_PHY_TOP_11AX_M2M_U0_CCAPER0_CCK_PER1_SHFT       0

/* =====================================================================================

  ---M2M_U0_PER1 (0x83000000 + 0x88)---

    LG_PER[31..0]                - (RW) LG: PER per rate
                                     [3:0] 6M,
                                     [7:4] 9M,
                                     [11:8] 12M,
                                     [15:12] 18M,
                                     [19:16] 24M,
                                     [23:20] 36M,
                                     [27:24] 48M,
                                     [31:28] 54M

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_U0_PER1_LG_PER_ADDR            WF_M2M_PHY_TOP_11AX_M2M_U0_PER1_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_U0_PER1_LG_PER_MASK            0xFFFFFFFF                // LG_PER[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_U0_PER1_LG_PER_SHFT            0

/* =====================================================================================

  ---M2M_U0_PER2 (0x83000000 + 0x8c)---

    BW20_PER0[31..0]             - (RW) BW20 (HT/VHT/HE): PER per rate 
                                     [3:0] MCS0,
                                     [7:4] MCS1,
                                     [11:8] MCS2,
                                     [15:12] MCS3,
                                     [19:16] MCS4,
                                     [23:20] MCS5,
                                     [27:24] MCS6,
                                     [31:28] MCS7

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_U0_PER2_BW20_PER0_ADDR         WF_M2M_PHY_TOP_11AX_M2M_U0_PER2_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_U0_PER2_BW20_PER0_MASK         0xFFFFFFFF                // BW20_PER0[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_U0_PER2_BW20_PER0_SHFT         0

/* =====================================================================================

  ---M2M_U0_PER3 (0x83000000 + 0x90)---

    BW40_PER0[31..0]             - (RW) BW40 (HT/VHT/HE): PER per rate 
                                     [3:0] MCS0,
                                     [7:4] MCS1,
                                     [11:8] MCS2,
                                     [15:12] MCS3,
                                     [19:16] MCS4,
                                     [23:20] MCS5,
                                     [27:24] MCS6,
                                     [31:28] MCS7

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_U0_PER3_BW40_PER0_ADDR         WF_M2M_PHY_TOP_11AX_M2M_U0_PER3_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_U0_PER3_BW40_PER0_MASK         0xFFFFFFFF                // BW40_PER0[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_U0_PER3_BW40_PER0_SHFT         0

/* =====================================================================================

  ---M2M_U0_PER4 (0x83000000 + 0x94)---

    BW80_PER0[31..0]             - (RW) BW80 (HT/VHT/HE): PER per rate
                                     [3:0] MCS0,
                                     [7:4] MCS1,
                                     [11:8] MCS2,
                                     [15:12] MCS3,
                                     [19:16] MCS4,
                                     [23:20] MCS5,
                                     [27:24] MCS6,
                                     [31:28] MCS7

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_U0_PER4_BW80_PER0_ADDR         WF_M2M_PHY_TOP_11AX_M2M_U0_PER4_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_U0_PER4_BW80_PER0_MASK         0xFFFFFFFF                // BW80_PER0[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_U0_PER4_BW80_PER0_SHFT         0

/* =====================================================================================

  ---M2M_U0_PER5 (0x83000000 + 0x98)---

    BW160_PER0[31..0]            - (RW) BW160 (HT/VHT/HE): PER per rate, 
                                     [3:0] MCS0,
                                     [7:4] MCS1,
                                     [11:8] MCS2,
                                     [15:12] MCS3,
                                     [19:16] MCS4,
                                     [23:20] MCS5,
                                     [27:24] MCS6,
                                     [31:28] MCS7

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_U0_PER5_BW160_PER0_ADDR        WF_M2M_PHY_TOP_11AX_M2M_U0_PER5_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_U0_PER5_BW160_PER0_MASK        0xFFFFFFFF                // BW160_PER0[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_U0_PER5_BW160_PER0_SHFT        0

/* =====================================================================================

  ---M2M_U0_PER6 (0x83000000 + 0x9c)---

    BW20_PER1[7..0]              - (RW) BW20 (VHT/HE): PER per rate,
                                     [3:0] MCS8,
                                     [7:4] MCS9
    BW40_PER1[15..8]             - (RW) BW40 (VHT/HE): PER per rate,
                                     [3:0] MCS8,
                                     [7:4] MCS9
    BW80_PER1[23..16]            - (RW) BW80 (VHT/HE): PER per rate,
                                     [3:0] MCS8,
                                     [7:4] MCS9
    BW160_PER1[31..24]           - (RW) BW160 (VHT/HE): PER per rate
                                     [3:0] MCS8,
                                     [7:4] MCS9

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_U0_PER6_BW160_PER1_ADDR        WF_M2M_PHY_TOP_11AX_M2M_U0_PER6_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_U0_PER6_BW160_PER1_MASK        0xFF000000                // BW160_PER1[31..24]
#define WF_M2M_PHY_TOP_11AX_M2M_U0_PER6_BW160_PER1_SHFT        24
#define WF_M2M_PHY_TOP_11AX_M2M_U0_PER6_BW80_PER1_ADDR         WF_M2M_PHY_TOP_11AX_M2M_U0_PER6_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_U0_PER6_BW80_PER1_MASK         0x00FF0000                // BW80_PER1[23..16]
#define WF_M2M_PHY_TOP_11AX_M2M_U0_PER6_BW80_PER1_SHFT         16
#define WF_M2M_PHY_TOP_11AX_M2M_U0_PER6_BW40_PER1_ADDR         WF_M2M_PHY_TOP_11AX_M2M_U0_PER6_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_U0_PER6_BW40_PER1_MASK         0x0000FF00                // BW40_PER1[15..8]
#define WF_M2M_PHY_TOP_11AX_M2M_U0_PER6_BW40_PER1_SHFT         8
#define WF_M2M_PHY_TOP_11AX_M2M_U0_PER6_BW20_PER1_ADDR         WF_M2M_PHY_TOP_11AX_M2M_U0_PER6_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_U0_PER6_BW20_PER1_MASK         0x000000FF                // BW20_PER1[7..0]
#define WF_M2M_PHY_TOP_11AX_M2M_U0_PER6_BW20_PER1_SHFT         0

/* =====================================================================================

  ---M2M_U0_PER7 (0x83000000 + 0xA0)---

    BW20_PER2[7..0]              - (RW) BW20 (HE): PER per rate,
                                     [3:0] MCS10,
                                     [7:4] MCS11
    BW40_PER2[15..8]             - (RW) BW40 (HE): PER per rate,
                                     [3:0] MCS10,
                                     [7:4] MCS11
    BW80_PER2[23..16]            - (RW) BW80 (HE): PER per rate,
                                     [3:0] MCS10,
                                     [7:4] MCS11
    BW160_PER2[31..24]           - (RW) BW160 (HE): PER per rate,
                                     [3:0] MCS10,
                                     [7:4] MCS11

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_U0_PER7_BW160_PER2_ADDR        WF_M2M_PHY_TOP_11AX_M2M_U0_PER7_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_U0_PER7_BW160_PER2_MASK        0xFF000000                // BW160_PER2[31..24]
#define WF_M2M_PHY_TOP_11AX_M2M_U0_PER7_BW160_PER2_SHFT        24
#define WF_M2M_PHY_TOP_11AX_M2M_U0_PER7_BW80_PER2_ADDR         WF_M2M_PHY_TOP_11AX_M2M_U0_PER7_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_U0_PER7_BW80_PER2_MASK         0x00FF0000                // BW80_PER2[23..16]
#define WF_M2M_PHY_TOP_11AX_M2M_U0_PER7_BW80_PER2_SHFT         16
#define WF_M2M_PHY_TOP_11AX_M2M_U0_PER7_BW40_PER2_ADDR         WF_M2M_PHY_TOP_11AX_M2M_U0_PER7_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_U0_PER7_BW40_PER2_MASK         0x0000FF00                // BW40_PER2[15..8]
#define WF_M2M_PHY_TOP_11AX_M2M_U0_PER7_BW40_PER2_SHFT         8
#define WF_M2M_PHY_TOP_11AX_M2M_U0_PER7_BW20_PER2_ADDR         WF_M2M_PHY_TOP_11AX_M2M_U0_PER7_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_U0_PER7_BW20_PER2_MASK         0x000000FF                // BW20_PER2[7..0]
#define WF_M2M_PHY_TOP_11AX_M2M_U0_PER7_BW20_PER2_SHFT         0

/* =====================================================================================

  ---M2M_RXVEC1 (0x83000000 + 0x210)---

    RXVEC1[31..0]                - (RO) TX side's TX Vector Common Group 1 DWORD_1[31:0]

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC1_RXVEC1_ADDR             WF_M2M_PHY_TOP_11AX_M2M_RXVEC1_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC1_RXVEC1_MASK             0xFFFFFFFF                // RXVEC1[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC1_RXVEC1_SHFT             0

/* =====================================================================================

  ---M2M_RXVEC2 (0x83000000 + 0x214)---

    RXVEC2[31..0]                - (RO) TX side's TX Vector Common Group 1 DWORD_1[63:32]

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC2_RXVEC2_ADDR             WF_M2M_PHY_TOP_11AX_M2M_RXVEC2_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC2_RXVEC2_MASK             0xFFFFFFFF                // RXVEC2[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC2_RXVEC2_SHFT             0

/* =====================================================================================

  ---M2M_RXVEC3 (0x83000000 + 0x218)---

    RXVEC3[31..0]                - (RO) TX side's TX Vector Common Group 1 DWORD_2[31:0]

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC3_RXVEC3_ADDR             WF_M2M_PHY_TOP_11AX_M2M_RXVEC3_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC3_RXVEC3_MASK             0xFFFFFFFF                // RXVEC3[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC3_RXVEC3_SHFT             0

/* =====================================================================================

  ---M2M_RXVEC4 (0x83000000 + 0x21c)---

    RXVEC4[31..0]                - (RO) TX side's TX Vector Common Group 1 DWORD_2[63:32]

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC4_RXVEC4_ADDR             WF_M2M_PHY_TOP_11AX_M2M_RXVEC4_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC4_RXVEC4_MASK             0xFFFFFFFF                // RXVEC4[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC4_RXVEC4_SHFT             0

/* =====================================================================================

  ---M2M_RXVEC5 (0x83000000 + 0x220)---

    RXVEC5[31..0]                - (RO) TX side's TX Vector Common Group 2 DWORD_1[31:0]

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC5_RXVEC5_ADDR             WF_M2M_PHY_TOP_11AX_M2M_RXVEC5_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC5_RXVEC5_MASK             0xFFFFFFFF                // RXVEC5[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC5_RXVEC5_SHFT             0

/* =====================================================================================

  ---M2M_RXVEC6 (0x83000000 + 0x224)---

    RXVEC6[31..0]                - (RO) TX side's TX Vector Common Group 2 DWORD_1[63:32]

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC6_RXVEC6_ADDR             WF_M2M_PHY_TOP_11AX_M2M_RXVEC6_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC6_RXVEC6_MASK             0xFFFFFFFF                // RXVEC6[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC6_RXVEC6_SHFT             0

/* =====================================================================================

  ---M2M_RXVEC7 (0x83000000 + 0x228)---

    RXVEC7[31..0]                - (RO) TX side's TX Vector Common Group 2 DWORD_2[31:0]

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC7_RXVEC7_ADDR             WF_M2M_PHY_TOP_11AX_M2M_RXVEC7_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC7_RXVEC7_MASK             0xFFFFFFFF                // RXVEC7[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC7_RXVEC7_SHFT             0

/* =====================================================================================

  ---M2M_RXVEC8 (0x83000000 + 0x22c)---

    RXVEC8[31..0]                - (RO) TX side's TX Vector Common Group 2 DWORD_2[63:32]

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC8_RXVEC8_ADDR             WF_M2M_PHY_TOP_11AX_M2M_RXVEC8_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC8_RXVEC8_MASK             0xFFFFFFFF                // RXVEC8[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC8_RXVEC8_SHFT             0

/* =====================================================================================

  ---M2M_RXVEC9 (0x83000000 + 0x230)---

    RXVEC9[31..0]                - (RO) TX side's TX Vector User0 Group 1 DWORD_1[31:0]

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC9_RXVEC9_ADDR             WF_M2M_PHY_TOP_11AX_M2M_RXVEC9_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC9_RXVEC9_MASK             0xFFFFFFFF                // RXVEC9[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC9_RXVEC9_SHFT             0

/* =====================================================================================

  ---M2M_RXVEC10 (0x83000000 + 0x234)---

    RXVEC10[31..0]               - (RO) TX side's TX Vector User0 Group 1 DWORD_1[63:32]

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC10_RXVEC10_ADDR           WF_M2M_PHY_TOP_11AX_M2M_RXVEC10_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC10_RXVEC10_MASK           0xFFFFFFFF                // RXVEC10[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC10_RXVEC10_SHFT           0

/* =====================================================================================

  ---M2M_RXVEC11 (0x83000000 + 0x238)---

    RXVEC11[31..0]               - (RO) TX side's TX Vector User0 Group 2 DWORD_1[31:0]

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC11_RXVEC11_ADDR           WF_M2M_PHY_TOP_11AX_M2M_RXVEC11_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC11_RXVEC11_MASK           0xFFFFFFFF                // RXVEC11[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC11_RXVEC11_SHFT           0

/* =====================================================================================

  ---M2M_RXVEC12 (0x83000000 + 0x23c)---

    RXVEC12[31..0]               - (RO) TX side's TX Vector User0 Group 2 DWORD_1[63:32]

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC12_RXVEC12_ADDR           WF_M2M_PHY_TOP_11AX_M2M_RXVEC12_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC12_RXVEC12_MASK           0xFFFFFFFF                // RXVEC12[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC12_RXVEC12_SHFT           0

/* =====================================================================================

  ---M2M_RXVEC13 (0x83000000 + 0x240)---

    RXVEC13[31..0]               - (RO) TX side's TX Vector User1 Group 1 DWORD_1[31:0]

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC13_RXVEC13_ADDR           WF_M2M_PHY_TOP_11AX_M2M_RXVEC13_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC13_RXVEC13_MASK           0xFFFFFFFF                // RXVEC13[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC13_RXVEC13_SHFT           0

/* =====================================================================================

  ---M2M_RXVEC14 (0x83000000 + 0x244)---

    RXVEC14[31..0]               - (RO) TX side's TX Vector User1 Group 1 DWORD_1[63:32]

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC14_RXVEC14_ADDR           WF_M2M_PHY_TOP_11AX_M2M_RXVEC14_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC14_RXVEC14_MASK           0xFFFFFFFF                // RXVEC14[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC14_RXVEC14_SHFT           0

/* =====================================================================================

  ---M2M_RXVEC15 (0x83000000 + 0x248)---

    RXVEC15[31..0]               - (RO) TX side's TX Vector User1 Group 2 DWORD_1[31:0]

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC15_RXVEC15_ADDR           WF_M2M_PHY_TOP_11AX_M2M_RXVEC15_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC15_RXVEC15_MASK           0xFFFFFFFF                // RXVEC15[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC15_RXVEC15_SHFT           0

/* =====================================================================================

  ---M2M_RXVEC16 (0x83000000 + 0x24c)---

    RXVEC16[31..0]               - (RO) TX side's TX Vector User1 Group 2 DWORD_1[63:32]

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC16_RXVEC16_ADDR           WF_M2M_PHY_TOP_11AX_M2M_RXVEC16_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC16_RXVEC16_MASK           0xFFFFFFFF                // RXVEC16[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC16_RXVEC16_SHFT           0

/* =====================================================================================

  ---M2M_RXVEC17 (0x83000000 + 0x250)---

    RXVEC17[31..0]               - (RO) TX side's TX Vector User2 Group 1 DWORD_1[31:0]

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC17_RXVEC17_ADDR           WF_M2M_PHY_TOP_11AX_M2M_RXVEC17_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC17_RXVEC17_MASK           0xFFFFFFFF                // RXVEC17[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC17_RXVEC17_SHFT           0

/* =====================================================================================

  ---M2M_RXVEC18 (0x83000000 + 0x254)---

    RXVEC18[31..0]               - (RO) TX side's TX Vector User2 Group 1 DWORD_1[63:32]

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC18_RXVEC18_ADDR           WF_M2M_PHY_TOP_11AX_M2M_RXVEC18_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC18_RXVEC18_MASK           0xFFFFFFFF                // RXVEC18[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC18_RXVEC18_SHFT           0

/* =====================================================================================

  ---M2M_RXVEC19 (0x83000000 + 0x258)---

    RXVEC19[31..0]               - (RO) TX side's TX Vector User2 Group 2 DWORD_1[31:0]

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC19_RXVEC19_ADDR           WF_M2M_PHY_TOP_11AX_M2M_RXVEC19_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC19_RXVEC19_MASK           0xFFFFFFFF                // RXVEC19[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC19_RXVEC19_SHFT           0

/* =====================================================================================

  ---M2M_RXVEC20 (0x83000000 + 0x25c)---

    RXVEC20[31..0]               - (RO) TX side's TX Vector User2 Group 2 DWORD_1[63:32]

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC20_RXVEC20_ADDR           WF_M2M_PHY_TOP_11AX_M2M_RXVEC20_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC20_RXVEC20_MASK           0xFFFFFFFF                // RXVEC20[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC20_RXVEC20_SHFT           0

/* =====================================================================================

  ---M2M_RXVEC21 (0x83000000 + 0x260)---

    RXVEC21[31..0]               - (RO) TX side's TX Vector User3 Group 1 DWORD_1[31:0]

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC21_RXVEC21_ADDR           WF_M2M_PHY_TOP_11AX_M2M_RXVEC21_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC21_RXVEC21_MASK           0xFFFFFFFF                // RXVEC21[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC21_RXVEC21_SHFT           0

/* =====================================================================================

  ---M2M_RXVEC22 (0x83000000 + 0x264)---

    RXVEC22[31..0]               - (RO) TX side's TX Vector User3 Group 1 DWORD_1[63:32]

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC22_RXVEC22_ADDR           WF_M2M_PHY_TOP_11AX_M2M_RXVEC22_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC22_RXVEC22_MASK           0xFFFFFFFF                // RXVEC22[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC22_RXVEC22_SHFT           0

/* =====================================================================================

  ---M2M_RXVEC23 (0x83000000 + 0x268)---

    RXVEC23[31..0]               - (RO) TX side's TX Vector User3 Group 2 DWORD_1[31:0]

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC23_RXVEC23_ADDR           WF_M2M_PHY_TOP_11AX_M2M_RXVEC23_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC23_RXVEC23_MASK           0xFFFFFFFF                // RXVEC23[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC23_RXVEC23_SHFT           0

/* =====================================================================================

  ---M2M_RXVEC24 (0x83000000 + 0x26c)---

    RXVEC24[31..0]               - (RO) TX side's TX Vector User3 Group 2 DWORD_1[63:32]

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC24_RXVEC24_ADDR           WF_M2M_PHY_TOP_11AX_M2M_RXVEC24_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC24_RXVEC24_MASK           0xFFFFFFFF                // RXVEC24[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC24_RXVEC24_SHFT           0

/* =====================================================================================

  ---M2M_FALSE_CCAPRI (0x83000000 + 0x454)---

    FALSE_CCA_CNT[23..0]         - (RW) The duration that False CCA asserts. Unit is 1 us. Total 24 bits. The max duration is 16 seconds.
    RESERVED24[29..24]           - (RO) Reserved bits
    FALSE_CCA_START[30]          - (RW) When this bit is set to 1'b1, M2M PHY model starts to assert CCA with CR_FALSE_CCA_CNT duration. M2M PHY model clears this bit when it finishes false CCA assertion.
    CCA_STATUS[31]               - (RO) 0: Primary CCA Low, 1: Primary CCA High

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_FALSE_CCAPRI_CCA_STATUS_ADDR   WF_M2M_PHY_TOP_11AX_M2M_FALSE_CCAPRI_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_FALSE_CCAPRI_CCA_STATUS_MASK   0x80000000                // CCA_STATUS[31]
#define WF_M2M_PHY_TOP_11AX_M2M_FALSE_CCAPRI_CCA_STATUS_SHFT   31
#define WF_M2M_PHY_TOP_11AX_M2M_FALSE_CCAPRI_FALSE_CCA_START_ADDR WF_M2M_PHY_TOP_11AX_M2M_FALSE_CCAPRI_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_FALSE_CCAPRI_FALSE_CCA_START_MASK 0x40000000                // FALSE_CCA_START[30]
#define WF_M2M_PHY_TOP_11AX_M2M_FALSE_CCAPRI_FALSE_CCA_START_SHFT 30
#define WF_M2M_PHY_TOP_11AX_M2M_FALSE_CCAPRI_FALSE_CCA_CNT_ADDR WF_M2M_PHY_TOP_11AX_M2M_FALSE_CCAPRI_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_FALSE_CCAPRI_FALSE_CCA_CNT_MASK 0x00FFFFFF                // FALSE_CCA_CNT[23..0]
#define WF_M2M_PHY_TOP_11AX_M2M_FALSE_CCAPRI_FALSE_CCA_CNT_SHFT 0

/* =====================================================================================

  ---M2M_FALSE_CCA20 (0x83000000 + 0x458)---

    FALSE_SEC20_CCA_CNT[23..0]   - (RW) The duration that False SEC20 CCA asserts. Unit is 1 us. Total 24 bits. The max duration is 16 seconds.
    RESERVED24[29..24]           - (RO) Reserved bits
    FALSE_SEC20_CCA_START[30]    - (RW) When this bit is set to 1'b1, M2M PHY model starts to assert SEC20 CCA with CR_FALSE_SEC20_CCA_CNT duration. M2M PHY model clears this bit when it finishes False SEC20 CCA assertion.
    SEC20_CCA_STATUS[31]         - (RO) 0: SEC20 CCA Low, 1: SEC20 CCA High

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_FALSE_CCA20_SEC20_CCA_STATUS_ADDR WF_M2M_PHY_TOP_11AX_M2M_FALSE_CCA20_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_FALSE_CCA20_SEC20_CCA_STATUS_MASK 0x80000000                // SEC20_CCA_STATUS[31]
#define WF_M2M_PHY_TOP_11AX_M2M_FALSE_CCA20_SEC20_CCA_STATUS_SHFT 31
#define WF_M2M_PHY_TOP_11AX_M2M_FALSE_CCA20_FALSE_SEC20_CCA_START_ADDR WF_M2M_PHY_TOP_11AX_M2M_FALSE_CCA20_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_FALSE_CCA20_FALSE_SEC20_CCA_START_MASK 0x40000000                // FALSE_SEC20_CCA_START[30]
#define WF_M2M_PHY_TOP_11AX_M2M_FALSE_CCA20_FALSE_SEC20_CCA_START_SHFT 30
#define WF_M2M_PHY_TOP_11AX_M2M_FALSE_CCA20_FALSE_SEC20_CCA_CNT_ADDR WF_M2M_PHY_TOP_11AX_M2M_FALSE_CCA20_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_FALSE_CCA20_FALSE_SEC20_CCA_CNT_MASK 0x00FFFFFF                // FALSE_SEC20_CCA_CNT[23..0]
#define WF_M2M_PHY_TOP_11AX_M2M_FALSE_CCA20_FALSE_SEC20_CCA_CNT_SHFT 0

/* =====================================================================================

  ---M2M_FALSE_CCA40 (0x83000000 + 0x45c)---

    FALSE_SEC40_CCA_CNT[23..0]   - (RW) The duration that False SEC40 CCA asserts. Unit is 1 us. Total 24 bits. The max duration is 16 seconds.
    RESERVED24[29..24]           - (RO) Reserved bits
    FALSE_SEC40_CCA_START[30]    - (RW) When this bit is set to 1'b1, M2M PHY model starts to assert SEC40 CCA with CR_FALSE_SEC40_CCA_CNT duration. M2M PHY model clears this bit when it finishes False SEC40 CCA assertion.
    SEC40_CCA_STATUS[31]         - (RO) 0: SEC40 CCA Low, 1: SEC40 CCA High

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_FALSE_CCA40_SEC40_CCA_STATUS_ADDR WF_M2M_PHY_TOP_11AX_M2M_FALSE_CCA40_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_FALSE_CCA40_SEC40_CCA_STATUS_MASK 0x80000000                // SEC40_CCA_STATUS[31]
#define WF_M2M_PHY_TOP_11AX_M2M_FALSE_CCA40_SEC40_CCA_STATUS_SHFT 31
#define WF_M2M_PHY_TOP_11AX_M2M_FALSE_CCA40_FALSE_SEC40_CCA_START_ADDR WF_M2M_PHY_TOP_11AX_M2M_FALSE_CCA40_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_FALSE_CCA40_FALSE_SEC40_CCA_START_MASK 0x40000000                // FALSE_SEC40_CCA_START[30]
#define WF_M2M_PHY_TOP_11AX_M2M_FALSE_CCA40_FALSE_SEC40_CCA_START_SHFT 30
#define WF_M2M_PHY_TOP_11AX_M2M_FALSE_CCA40_FALSE_SEC40_CCA_CNT_ADDR WF_M2M_PHY_TOP_11AX_M2M_FALSE_CCA40_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_FALSE_CCA40_FALSE_SEC40_CCA_CNT_MASK 0x00FFFFFF                // FALSE_SEC40_CCA_CNT[23..0]
#define WF_M2M_PHY_TOP_11AX_M2M_FALSE_CCA40_FALSE_SEC40_CCA_CNT_SHFT 0

/* =====================================================================================

  ---M2M_FALSE_CCA80 (0x83000000 + 0x460)---

    FALSE_SEC80_CCA_CNT[23..0]   - (RW) The duration that False SEC80 CCA asserts. Unit is 1 us. Total 24 bits. The max duration is 16 seconds.
    RESERVED24[29..24]           - (RO) Reserved bits
    FALSE_SEC80_CCA_START[30]    - (RW) When this bit is set to 1'b1, M2M PHY model starts to assert SEC80 CCA with CR_FALSE_SEC80_CCA_CNT duration. M2M PHY model clears this bit when it finishes False SEC80 CCA assertion.
    SEC80_CCA_STATUS[31]         - (RO) 0: SEC80 CCA Low, 1: SEC80 CCA High

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_FALSE_CCA80_SEC80_CCA_STATUS_ADDR WF_M2M_PHY_TOP_11AX_M2M_FALSE_CCA80_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_FALSE_CCA80_SEC80_CCA_STATUS_MASK 0x80000000                // SEC80_CCA_STATUS[31]
#define WF_M2M_PHY_TOP_11AX_M2M_FALSE_CCA80_SEC80_CCA_STATUS_SHFT 31
#define WF_M2M_PHY_TOP_11AX_M2M_FALSE_CCA80_FALSE_SEC80_CCA_START_ADDR WF_M2M_PHY_TOP_11AX_M2M_FALSE_CCA80_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_FALSE_CCA80_FALSE_SEC80_CCA_START_MASK 0x40000000                // FALSE_SEC80_CCA_START[30]
#define WF_M2M_PHY_TOP_11AX_M2M_FALSE_CCA80_FALSE_SEC80_CCA_START_SHFT 30
#define WF_M2M_PHY_TOP_11AX_M2M_FALSE_CCA80_FALSE_SEC80_CCA_CNT_ADDR WF_M2M_PHY_TOP_11AX_M2M_FALSE_CCA80_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_FALSE_CCA80_FALSE_SEC80_CCA_CNT_MASK 0x00FFFFFF                // FALSE_SEC80_CCA_CNT[23..0]
#define WF_M2M_PHY_TOP_11AX_M2M_FALSE_CCA80_FALSE_SEC80_CCA_CNT_SHFT 0

/* =====================================================================================

  ---M2M_TXV1 (0x83000000 + 0x630)---

    TXVEC1[31..0]                - (RO) TX Vector Common Group 1 DWORD_1[31:0]

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_TXV1_TXVEC1_ADDR               WF_M2M_PHY_TOP_11AX_M2M_TXV1_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_TXV1_TXVEC1_MASK               0xFFFFFFFF                // TXVEC1[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_TXV1_TXVEC1_SHFT               0

/* =====================================================================================

  ---M2M_TXV2 (0x83000000 + 0x634)---

    TXVEC2[31..0]                - (RO) TX Vector Common Group 1 DWORD_1[63:32]

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_TXV2_TXVEC2_ADDR               WF_M2M_PHY_TOP_11AX_M2M_TXV2_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_TXV2_TXVEC2_MASK               0xFFFFFFFF                // TXVEC2[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_TXV2_TXVEC2_SHFT               0

/* =====================================================================================

  ---M2M_TXV3 (0x83000000 + 0x638)---

    TXVEC3[31..0]                - (RO) TX Vector Common Group 1 DWORD_2[31:0]

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_TXV3_TXVEC3_ADDR               WF_M2M_PHY_TOP_11AX_M2M_TXV3_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_TXV3_TXVEC3_MASK               0xFFFFFFFF                // TXVEC3[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_TXV3_TXVEC3_SHFT               0

/* =====================================================================================

  ---M2M_TXV4 (0x83000000 + 0x63c)---

    TXVEC4[31..0]                - (RO) TX Vector Common Group 1 DWORD_2[63:32]

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_TXV4_TXVEC4_ADDR               WF_M2M_PHY_TOP_11AX_M2M_TXV4_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_TXV4_TXVEC4_MASK               0xFFFFFFFF                // TXVEC4[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_TXV4_TXVEC4_SHFT               0

/* =====================================================================================

  ---M2M_TXV5 (0x83000000 + 0x640)---

    TXVEC5[31..0]                - (RO) TX Vector Common Group 2 DWORD_1[31:0]

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_TXV5_TXVEC5_ADDR               WF_M2M_PHY_TOP_11AX_M2M_TXV5_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_TXV5_TXVEC5_MASK               0xFFFFFFFF                // TXVEC5[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_TXV5_TXVEC5_SHFT               0

/* =====================================================================================

  ---M2M_TXV6 (0x83000000 + 0x644)---

    TXVEC6[31..0]                - (RO) TX Vector Common Group 2 DWORD_1[63:32]

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_TXV6_TXVEC6_ADDR               WF_M2M_PHY_TOP_11AX_M2M_TXV6_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_TXV6_TXVEC6_MASK               0xFFFFFFFF                // TXVEC6[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_TXV6_TXVEC6_SHFT               0

/* =====================================================================================

  ---M2M_TXV7 (0x83000000 + 0x648)---

    TXVEC7[31..0]                - (RO) TX Vector Common Group 2 DWORD_2[31:0]

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_TXV7_TXVEC7_ADDR               WF_M2M_PHY_TOP_11AX_M2M_TXV7_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_TXV7_TXVEC7_MASK               0xFFFFFFFF                // TXVEC7[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_TXV7_TXVEC7_SHFT               0

/* =====================================================================================

  ---M2M_TXV8 (0x83000000 + 0x64c)---

    TXVEC8[31..0]                - (RO) TX Vector Common Group 2 DWORD_2[63:32]

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_TXV8_TXVEC8_ADDR               WF_M2M_PHY_TOP_11AX_M2M_TXV8_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_TXV8_TXVEC8_MASK               0xFFFFFFFF                // TXVEC8[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_TXV8_TXVEC8_SHFT               0

/* =====================================================================================

  ---M2M_TXV9 (0x83000000 + 0x650)---

    TXVEC9[31..0]                - (RO) TX Vector User0 Group 1 DWORD_1[31:0]

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_TXV9_TXVEC9_ADDR               WF_M2M_PHY_TOP_11AX_M2M_TXV9_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_TXV9_TXVEC9_MASK               0xFFFFFFFF                // TXVEC9[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_TXV9_TXVEC9_SHFT               0

/* =====================================================================================

  ---M2M_TXV10 (0x83000000 + 0x654)---

    TXVEC10[31..0]               - (RO) TX Vector User0 Group 1 DWORD_1[63:32]

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_TXV10_TXVEC10_ADDR             WF_M2M_PHY_TOP_11AX_M2M_TXV10_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_TXV10_TXVEC10_MASK             0xFFFFFFFF                // TXVEC10[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_TXV10_TXVEC10_SHFT             0

/* =====================================================================================

  ---M2M_TXV11 (0x83000000 + 0x658)---

    TXVEC11[31..0]               - (RO) TX Vector User0 Group 2 DWORD_1[31:0]

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_TXV11_TXVEC11_ADDR             WF_M2M_PHY_TOP_11AX_M2M_TXV11_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_TXV11_TXVEC11_MASK             0xFFFFFFFF                // TXVEC11[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_TXV11_TXVEC11_SHFT             0

/* =====================================================================================

  ---M2M_TXV12 (0x83000000 + 0x65c)---

    TXVEC12[31..0]               - (RO) TX Vector User0 Group 2 DWORD_1[63:32]

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_TXV12_TXVEC12_ADDR             WF_M2M_PHY_TOP_11AX_M2M_TXV12_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_TXV12_TXVEC12_MASK             0xFFFFFFFF                // TXVEC12[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_TXV12_TXVEC12_SHFT             0

/* =====================================================================================

  ---M2M_TXV13 (0x83000000 + 0x660)---

    TXVEC13[31..0]               - (RO) TX Vector User1 Group 1 DWORD_1[31:0]

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_TXV13_TXVEC13_ADDR             WF_M2M_PHY_TOP_11AX_M2M_TXV13_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_TXV13_TXVEC13_MASK             0xFFFFFFFF                // TXVEC13[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_TXV13_TXVEC13_SHFT             0

/* =====================================================================================

  ---M2M_TXV14 (0x83000000 + 0x664)---

    TXVEC14[31..0]               - (RO) TX Vector User1 Group 1 DWORD_1[63:32]

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_TXV14_TXVEC14_ADDR             WF_M2M_PHY_TOP_11AX_M2M_TXV14_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_TXV14_TXVEC14_MASK             0xFFFFFFFF                // TXVEC14[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_TXV14_TXVEC14_SHFT             0

/* =====================================================================================

  ---M2M_TXV15 (0x83000000 + 0x668)---

    TXVEC15[31..0]               - (RO) TX Vector User1 Group 2 DWORD_1[31:0]

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_TXV15_TXVEC15_ADDR             WF_M2M_PHY_TOP_11AX_M2M_TXV15_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_TXV15_TXVEC15_MASK             0xFFFFFFFF                // TXVEC15[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_TXV15_TXVEC15_SHFT             0

/* =====================================================================================

  ---M2M_TXV16 (0x83000000 + 0x66c)---

    TXVEC16[31..0]               - (RO) TX Vector User1 Group 2 DWORD_1[63:32]

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_TXV16_TXVEC16_ADDR             WF_M2M_PHY_TOP_11AX_M2M_TXV16_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_TXV16_TXVEC16_MASK             0xFFFFFFFF                // TXVEC16[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_TXV16_TXVEC16_SHFT             0

/* =====================================================================================

  ---M2M_TXV17 (0x83000000 + 0x670)---

    TXVEC17[31..0]               - (RO) TX Vector User2 Group 1 DWORD_1[31:0]

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_TXV17_TXVEC17_ADDR             WF_M2M_PHY_TOP_11AX_M2M_TXV17_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_TXV17_TXVEC17_MASK             0xFFFFFFFF                // TXVEC17[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_TXV17_TXVEC17_SHFT             0

/* =====================================================================================

  ---M2M_TXV18 (0x83000000 + 0x674)---

    TXVEC18[31..0]               - (RO) TX Vector User2 Group 1 DWORD_1[63:32]

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_TXV18_TXVEC18_ADDR             WF_M2M_PHY_TOP_11AX_M2M_TXV18_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_TXV18_TXVEC18_MASK             0xFFFFFFFF                // TXVEC18[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_TXV18_TXVEC18_SHFT             0

/* =====================================================================================

  ---M2M_TXV19 (0x83000000 + 0x678)---

    TXVEC19[31..0]               - (RO) TX Vector User2 Group 2 DWORD_1[31:0]

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_TXV19_TXVEC19_ADDR             WF_M2M_PHY_TOP_11AX_M2M_TXV19_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_TXV19_TXVEC19_MASK             0xFFFFFFFF                // TXVEC19[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_TXV19_TXVEC19_SHFT             0

/* =====================================================================================

  ---M2M_TXV20 (0x83000000 + 0x67c)---

    TXVEC20[31..0]               - (RO) TX Vector User2 Group 2 DWORD_1[63:32]

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_TXV20_TXVEC20_ADDR             WF_M2M_PHY_TOP_11AX_M2M_TXV20_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_TXV20_TXVEC20_MASK             0xFFFFFFFF                // TXVEC20[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_TXV20_TXVEC20_SHFT             0

/* =====================================================================================

  ---M2M_TXV21 (0x83000000 + 0x680)---

    TXVEC21[31..0]               - (RO) TX Vector User3 Group 1 DWORD_1[31:0]

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_TXV21_TXVEC21_ADDR             WF_M2M_PHY_TOP_11AX_M2M_TXV21_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_TXV21_TXVEC21_MASK             0xFFFFFFFF                // TXVEC21[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_TXV21_TXVEC21_SHFT             0

/* =====================================================================================

  ---M2M_TXV22 (0x83000000 + 0x684)---

    TXVEC22[31..0]               - (RO) TX Vector User3 Group 1 DWORD_1[63:32]

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_TXV22_TXVEC22_ADDR             WF_M2M_PHY_TOP_11AX_M2M_TXV22_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_TXV22_TXVEC22_MASK             0xFFFFFFFF                // TXVEC22[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_TXV22_TXVEC22_SHFT             0

/* =====================================================================================

  ---M2M_TXV23 (0x83000000 + 0x688)---

    TXVEC23[31..0]               - (RO) TX Vector User3 Group 2 DWORD_1[31:0]

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_TXV23_TXVEC23_ADDR             WF_M2M_PHY_TOP_11AX_M2M_TXV23_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_TXV23_TXVEC23_MASK             0xFFFFFFFF                // TXVEC23[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_TXV23_TXVEC23_SHFT             0

/* =====================================================================================

  ---M2M_TXV24 (0x83000000 + 0x68c)---

    TXVEC24[31..0]               - (RO) TX Vector User3 Group 2 DWORD_1[63:32]

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_TXV24_TXVEC24_ADDR             WF_M2M_PHY_TOP_11AX_M2M_TXV24_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_TXV24_TXVEC24_MASK             0xFFFFFFFF                // TXVEC24[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_TXV24_TXVEC24_SHFT             0

/* =====================================================================================

  ---M2M_TPC (0x83000000 + 0xC08)---

    PHY2MAC_TXPWR[7..0]          - (RW) TX power value to MAC
    PHY2MAC_UPH[12..8]           - (RW) UPH value to MAC
    PHY2MAC_MINTXPWR[13]         - (RW) MIN TX Power flag to MAC
    TPC_Value_RSV[31..14]        - (RW) Reserved

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_TPC_TPC_Value_RSV_ADDR         WF_M2M_PHY_TOP_11AX_M2M_TPC_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_TPC_TPC_Value_RSV_MASK         0xFFFFC000                // TPC_Value_RSV[31..14]
#define WF_M2M_PHY_TOP_11AX_M2M_TPC_TPC_Value_RSV_SHFT         14
#define WF_M2M_PHY_TOP_11AX_M2M_TPC_PHY2MAC_MINTXPWR_ADDR      WF_M2M_PHY_TOP_11AX_M2M_TPC_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_TPC_PHY2MAC_MINTXPWR_MASK      0x00002000                // PHY2MAC_MINTXPWR[13]
#define WF_M2M_PHY_TOP_11AX_M2M_TPC_PHY2MAC_MINTXPWR_SHFT      13
#define WF_M2M_PHY_TOP_11AX_M2M_TPC_PHY2MAC_UPH_ADDR           WF_M2M_PHY_TOP_11AX_M2M_TPC_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_TPC_PHY2MAC_UPH_MASK           0x00001F00                // PHY2MAC_UPH[12..8]
#define WF_M2M_PHY_TOP_11AX_M2M_TPC_PHY2MAC_UPH_SHFT           8
#define WF_M2M_PHY_TOP_11AX_M2M_TPC_PHY2MAC_TXPWR_ADDR         WF_M2M_PHY_TOP_11AX_M2M_TPC_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_TPC_PHY2MAC_TXPWR_MASK         0x000000FF                // PHY2MAC_TXPWR[7..0]
#define WF_M2M_PHY_TOP_11AX_M2M_TPC_PHY2MAC_TXPWR_SHFT         0

/* =====================================================================================

  ---M2M_PER_BYTECNT (0x83000000 + 0xC64)---

    PER_BYTE_CNT[23..0]          - (RW) Byte count number for PER
    PER_BYTE_CNT_RSV[30..24]     - (RW) Reserved
    PER_BYTE_CNT_EN[31]          - (RW) Enable PER by byte count

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_PER_BYTECNT_PER_BYTE_CNT_EN_ADDR WF_M2M_PHY_TOP_11AX_M2M_PER_BYTECNT_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_PER_BYTECNT_PER_BYTE_CNT_EN_MASK 0x80000000                // PER_BYTE_CNT_EN[31]
#define WF_M2M_PHY_TOP_11AX_M2M_PER_BYTECNT_PER_BYTE_CNT_EN_SHFT 31
#define WF_M2M_PHY_TOP_11AX_M2M_PER_BYTECNT_PER_BYTE_CNT_RSV_ADDR WF_M2M_PHY_TOP_11AX_M2M_PER_BYTECNT_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_PER_BYTECNT_PER_BYTE_CNT_RSV_MASK 0x7F000000                // PER_BYTE_CNT_RSV[30..24]
#define WF_M2M_PHY_TOP_11AX_M2M_PER_BYTECNT_PER_BYTE_CNT_RSV_SHFT 24
#define WF_M2M_PHY_TOP_11AX_M2M_PER_BYTECNT_PER_BYTE_CNT_ADDR  WF_M2M_PHY_TOP_11AX_M2M_PER_BYTECNT_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_PER_BYTECNT_PER_BYTE_CNT_MASK  0x00FFFFFF                // PER_BYTE_CNT[23..0]
#define WF_M2M_PHY_TOP_11AX_M2M_PER_BYTECNT_PER_BYTE_CNT_SHFT  0

/* =====================================================================================

  ---M2M_TXMON_CTRL (0x83000000 + 0x1000)---

    TXMON_PPDU_DW_CNT[7..0]      - (RW) DW monitor count for each PPDU
    M2M_TXMON_CTRL_RSV[15..8]    - (RW) Reserved
    TX_MON_UID_FIFO_RST[16]      - (RW) Reset UID's FIFO
    TX_MON_PPDU_FIFO_RST[17]     - (RW) Reset PPDU's FIFO
    M2M_TXMON_CTRL_RSV_2[23..18] - (RW) Reserved
    TX_MON_UID_ENABLE[24]        - (RW) Enable TX UID monitor
    TX_MON_PPDU_ENABLE[25]       - (RW) Enable TX PPDU monitor
    M2M_TXMON_CTRL_RSV_3[31..26] - (RW) Reserved

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_CTRL_M2M_TXMON_CTRL_RSV_3_ADDR WF_M2M_PHY_TOP_11AX_M2M_TXMON_CTRL_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_CTRL_M2M_TXMON_CTRL_RSV_3_MASK 0xFC000000                // M2M_TXMON_CTRL_RSV_3[31..26]
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_CTRL_M2M_TXMON_CTRL_RSV_3_SHFT 26
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_CTRL_TX_MON_PPDU_ENABLE_ADDR WF_M2M_PHY_TOP_11AX_M2M_TXMON_CTRL_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_CTRL_TX_MON_PPDU_ENABLE_MASK 0x02000000                // TX_MON_PPDU_ENABLE[25]
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_CTRL_TX_MON_PPDU_ENABLE_SHFT 25
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_CTRL_TX_MON_UID_ENABLE_ADDR WF_M2M_PHY_TOP_11AX_M2M_TXMON_CTRL_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_CTRL_TX_MON_UID_ENABLE_MASK 0x01000000                // TX_MON_UID_ENABLE[24]
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_CTRL_TX_MON_UID_ENABLE_SHFT 24
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_CTRL_M2M_TXMON_CTRL_RSV_2_ADDR WF_M2M_PHY_TOP_11AX_M2M_TXMON_CTRL_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_CTRL_M2M_TXMON_CTRL_RSV_2_MASK 0x00FC0000                // M2M_TXMON_CTRL_RSV_2[23..18]
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_CTRL_M2M_TXMON_CTRL_RSV_2_SHFT 18
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_CTRL_TX_MON_PPDU_FIFO_RST_ADDR WF_M2M_PHY_TOP_11AX_M2M_TXMON_CTRL_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_CTRL_TX_MON_PPDU_FIFO_RST_MASK 0x00020000                // TX_MON_PPDU_FIFO_RST[17]
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_CTRL_TX_MON_PPDU_FIFO_RST_SHFT 17
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_CTRL_TX_MON_UID_FIFO_RST_ADDR WF_M2M_PHY_TOP_11AX_M2M_TXMON_CTRL_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_CTRL_TX_MON_UID_FIFO_RST_MASK 0x00010000                // TX_MON_UID_FIFO_RST[16]
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_CTRL_TX_MON_UID_FIFO_RST_SHFT 16
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_CTRL_M2M_TXMON_CTRL_RSV_ADDR WF_M2M_PHY_TOP_11AX_M2M_TXMON_CTRL_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_CTRL_M2M_TXMON_CTRL_RSV_MASK 0x0000FF00                // M2M_TXMON_CTRL_RSV[15..8]
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_CTRL_M2M_TXMON_CTRL_RSV_SHFT 8
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_CTRL_TXMON_PPDU_DW_CNT_ADDR WF_M2M_PHY_TOP_11AX_M2M_TXMON_CTRL_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_CTRL_TXMON_PPDU_DW_CNT_MASK 0x000000FF                // TXMON_PPDU_DW_CNT[7..0]
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_CTRL_TXMON_PPDU_DW_CNT_SHFT 0

/* =====================================================================================

  ---M2M_TXMON_UID_DATA (0x83000000 + 0x1004)---

    TXMON_UID_DATA[31..0]        - (RO) Data port of TX UID monitor FIFO.

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_UID_DATA_TXMON_UID_DATA_ADDR WF_M2M_PHY_TOP_11AX_M2M_TXMON_UID_DATA_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_UID_DATA_TXMON_UID_DATA_MASK 0xFFFFFFFF                // TXMON_UID_DATA[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_UID_DATA_TXMON_UID_DATA_SHFT 0

/* =====================================================================================

  ---M2M_TXMON_UID_STATUS (0x83000000 + 0x1008)---

    TXMON_UID_FIFO_WPTR[8..0]    - (RO) Current FIFO write count
    TXMON_UID_FIFO_RSV[15..9]    - (RO) Reserved
    TXMON_UID_FIFO_RPTR[24..16]  - (RO) Remained FIFO read count
    TXMON_UID_FIFO_RSV_2[29..25] - (RO) Reserved
    TXMON_UID_FIFO_EMPTY[30]     - (RO) FIFO empty status of TX UID monitor FIFO
    TXMON_UID_FIFO_FULL[31]      - (RO) FIFO full status of TX UID monitor FIFO

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_UID_STATUS_TXMON_UID_FIFO_FULL_ADDR WF_M2M_PHY_TOP_11AX_M2M_TXMON_UID_STATUS_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_UID_STATUS_TXMON_UID_FIFO_FULL_MASK 0x80000000                // TXMON_UID_FIFO_FULL[31]
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_UID_STATUS_TXMON_UID_FIFO_FULL_SHFT 31
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_UID_STATUS_TXMON_UID_FIFO_EMPTY_ADDR WF_M2M_PHY_TOP_11AX_M2M_TXMON_UID_STATUS_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_UID_STATUS_TXMON_UID_FIFO_EMPTY_MASK 0x40000000                // TXMON_UID_FIFO_EMPTY[30]
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_UID_STATUS_TXMON_UID_FIFO_EMPTY_SHFT 30
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_UID_STATUS_TXMON_UID_FIFO_RSV_2_ADDR WF_M2M_PHY_TOP_11AX_M2M_TXMON_UID_STATUS_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_UID_STATUS_TXMON_UID_FIFO_RSV_2_MASK 0x3E000000                // TXMON_UID_FIFO_RSV_2[29..25]
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_UID_STATUS_TXMON_UID_FIFO_RSV_2_SHFT 25
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_UID_STATUS_TXMON_UID_FIFO_RPTR_ADDR WF_M2M_PHY_TOP_11AX_M2M_TXMON_UID_STATUS_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_UID_STATUS_TXMON_UID_FIFO_RPTR_MASK 0x01FF0000                // TXMON_UID_FIFO_RPTR[24..16]
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_UID_STATUS_TXMON_UID_FIFO_RPTR_SHFT 16
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_UID_STATUS_TXMON_UID_FIFO_RSV_ADDR WF_M2M_PHY_TOP_11AX_M2M_TXMON_UID_STATUS_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_UID_STATUS_TXMON_UID_FIFO_RSV_MASK 0x0000FE00                // TXMON_UID_FIFO_RSV[15..9]
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_UID_STATUS_TXMON_UID_FIFO_RSV_SHFT 9
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_UID_STATUS_TXMON_UID_FIFO_WPTR_ADDR WF_M2M_PHY_TOP_11AX_M2M_TXMON_UID_STATUS_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_UID_STATUS_TXMON_UID_FIFO_WPTR_MASK 0x000001FF                // TXMON_UID_FIFO_WPTR[8..0]
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_UID_STATUS_TXMON_UID_FIFO_WPTR_SHFT 0

/* =====================================================================================

  ---M2M_TXMON_PPDU_DATA (0x83000000 + 0x100C)---

    TXMON_PPDU_DATA[31..0]       - (RO) Data port of TX PPDU monitor FIFO.

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_PPDU_DATA_TXMON_PPDU_DATA_ADDR WF_M2M_PHY_TOP_11AX_M2M_TXMON_PPDU_DATA_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_PPDU_DATA_TXMON_PPDU_DATA_MASK 0xFFFFFFFF                // TXMON_PPDU_DATA[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_PPDU_DATA_TXMON_PPDU_DATA_SHFT 0

/* =====================================================================================

  ---M2M_TXMON_PPDU_STATUS (0x83000000 + 0x1010)---

    TXMON_PPDU_FIFO_WPTR[8..0]   - (RO) Current PPDU FIFO write count
    TXMON_PPDU_FIFO_RSV[15..9]   - (RO) Reserved
    TXMON_PPDU_FIFO_RPTR[24..16] - (RO) Remained PPDU FIFO read count
    TXMON_PPDU_FIFO_RSV_2[29..25] - (RO) Reserved
    TXMON_PPDU_FIFO_EMPTY[30]    - (RO) FIFO empty status of TX PPDU monitor FIFO
    TXMON_PPDU_FIFO_FULL[31]     - (RO) FIFO full status of TX PPDU monitor FIFO

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_PPDU_STATUS_TXMON_PPDU_FIFO_FULL_ADDR WF_M2M_PHY_TOP_11AX_M2M_TXMON_PPDU_STATUS_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_PPDU_STATUS_TXMON_PPDU_FIFO_FULL_MASK 0x80000000                // TXMON_PPDU_FIFO_FULL[31]
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_PPDU_STATUS_TXMON_PPDU_FIFO_FULL_SHFT 31
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_PPDU_STATUS_TXMON_PPDU_FIFO_EMPTY_ADDR WF_M2M_PHY_TOP_11AX_M2M_TXMON_PPDU_STATUS_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_PPDU_STATUS_TXMON_PPDU_FIFO_EMPTY_MASK 0x40000000                // TXMON_PPDU_FIFO_EMPTY[30]
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_PPDU_STATUS_TXMON_PPDU_FIFO_EMPTY_SHFT 30
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_PPDU_STATUS_TXMON_PPDU_FIFO_RSV_2_ADDR WF_M2M_PHY_TOP_11AX_M2M_TXMON_PPDU_STATUS_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_PPDU_STATUS_TXMON_PPDU_FIFO_RSV_2_MASK 0x3E000000                // TXMON_PPDU_FIFO_RSV_2[29..25]
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_PPDU_STATUS_TXMON_PPDU_FIFO_RSV_2_SHFT 25
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_PPDU_STATUS_TXMON_PPDU_FIFO_RPTR_ADDR WF_M2M_PHY_TOP_11AX_M2M_TXMON_PPDU_STATUS_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_PPDU_STATUS_TXMON_PPDU_FIFO_RPTR_MASK 0x01FF0000                // TXMON_PPDU_FIFO_RPTR[24..16]
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_PPDU_STATUS_TXMON_PPDU_FIFO_RPTR_SHFT 16
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_PPDU_STATUS_TXMON_PPDU_FIFO_RSV_ADDR WF_M2M_PHY_TOP_11AX_M2M_TXMON_PPDU_STATUS_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_PPDU_STATUS_TXMON_PPDU_FIFO_RSV_MASK 0x0000FE00                // TXMON_PPDU_FIFO_RSV[15..9]
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_PPDU_STATUS_TXMON_PPDU_FIFO_RSV_SHFT 9
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_PPDU_STATUS_TXMON_PPDU_FIFO_WPTR_ADDR WF_M2M_PHY_TOP_11AX_M2M_TXMON_PPDU_STATUS_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_PPDU_STATUS_TXMON_PPDU_FIFO_WPTR_MASK 0x000001FF                // TXMON_PPDU_FIFO_WPTR[8..0]
#define WF_M2M_PHY_TOP_11AX_M2M_TXMON_PPDU_STATUS_TXMON_PPDU_FIFO_WPTR_SHFT 0

/* =====================================================================================

  ---M2M_TXVEC_EXT1_U0 (0x83000000 + 0x1040)---

    TXVEC_EXT1_U0[31..0]         - (RO) TX Vector EXT1 (U0)

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_TXVEC_EXT1_U0_TXVEC_EXT1_U0_ADDR WF_M2M_PHY_TOP_11AX_M2M_TXVEC_EXT1_U0_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_TXVEC_EXT1_U0_TXVEC_EXT1_U0_MASK 0xFFFFFFFF                // TXVEC_EXT1_U0[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_TXVEC_EXT1_U0_TXVEC_EXT1_U0_SHFT 0

/* =====================================================================================

  ---M2M_TXVEC_EXT2_U0 (0x83000000 + 0x1044)---

    TXVEC_EXT2_U0[31..0]         - (RO) TX Vector EXT2 (U0)

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_TXVEC_EXT2_U0_TXVEC_EXT2_U0_ADDR WF_M2M_PHY_TOP_11AX_M2M_TXVEC_EXT2_U0_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_TXVEC_EXT2_U0_TXVEC_EXT2_U0_MASK 0xFFFFFFFF                // TXVEC_EXT2_U0[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_TXVEC_EXT2_U0_TXVEC_EXT2_U0_SHFT 0

/* =====================================================================================

  ---M2M_TXVEC_EXT3_U0 (0x83000000 + 0x1048)---

    TXVEC_EXT3_U0[31..0]         - (RO) TX Vector EXT3 (U0)

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_TXVEC_EXT3_U0_TXVEC_EXT3_U0_ADDR WF_M2M_PHY_TOP_11AX_M2M_TXVEC_EXT3_U0_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_TXVEC_EXT3_U0_TXVEC_EXT3_U0_MASK 0xFFFFFFFF                // TXVEC_EXT3_U0[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_TXVEC_EXT3_U0_TXVEC_EXT3_U0_SHFT 0

/* =====================================================================================

  ---M2M_TXVEC_EXT1_U1 (0x83000000 + 0x104c)---

    TXVEC_EXT1_U1[31..0]         - (RO) TX Vector EXT1 (U1)

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_TXVEC_EXT1_U1_TXVEC_EXT1_U1_ADDR WF_M2M_PHY_TOP_11AX_M2M_TXVEC_EXT1_U1_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_TXVEC_EXT1_U1_TXVEC_EXT1_U1_MASK 0xFFFFFFFF                // TXVEC_EXT1_U1[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_TXVEC_EXT1_U1_TXVEC_EXT1_U1_SHFT 0

/* =====================================================================================

  ---M2M_TXVEC_EXT2_U1 (0x83000000 + 0x1050)---

    TXVEC_EXT2_U1[31..0]         - (RO) TX Vector EXT2 (U1)

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_TXVEC_EXT2_U1_TXVEC_EXT2_U1_ADDR WF_M2M_PHY_TOP_11AX_M2M_TXVEC_EXT2_U1_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_TXVEC_EXT2_U1_TXVEC_EXT2_U1_MASK 0xFFFFFFFF                // TXVEC_EXT2_U1[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_TXVEC_EXT2_U1_TXVEC_EXT2_U1_SHFT 0

/* =====================================================================================

  ---M2M_TXVEC_EXT3_U1 (0x83000000 + 0x1054)---

    TXVEC_EXT3_U1[31..0]         - (RO) TX Vector EXT3 (U1)

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_TXVEC_EXT3_U1_TXVEC_EXT3_U1_ADDR WF_M2M_PHY_TOP_11AX_M2M_TXVEC_EXT3_U1_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_TXVEC_EXT3_U1_TXVEC_EXT3_U1_MASK 0xFFFFFFFF                // TXVEC_EXT3_U1[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_TXVEC_EXT3_U1_TXVEC_EXT3_U1_SHFT 0

/* =====================================================================================

  ---M2M_TXVEC_EXT1_U2 (0x83000000 + 0x1058)---

    TXVEC_EXT1_U2[31..0]         - (RO) TX Vector EXT1 (U2)

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_TXVEC_EXT1_U2_TXVEC_EXT1_U2_ADDR WF_M2M_PHY_TOP_11AX_M2M_TXVEC_EXT1_U2_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_TXVEC_EXT1_U2_TXVEC_EXT1_U2_MASK 0xFFFFFFFF                // TXVEC_EXT1_U2[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_TXVEC_EXT1_U2_TXVEC_EXT1_U2_SHFT 0

/* =====================================================================================

  ---M2M_TXVEC_EXT2_U2 (0x83000000 + 0x105c)---

    TXVEC_EXT2_U2[31..0]         - (RO) TX Vector EXT2 (U2)

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_TXVEC_EXT2_U2_TXVEC_EXT2_U2_ADDR WF_M2M_PHY_TOP_11AX_M2M_TXVEC_EXT2_U2_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_TXVEC_EXT2_U2_TXVEC_EXT2_U2_MASK 0xFFFFFFFF                // TXVEC_EXT2_U2[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_TXVEC_EXT2_U2_TXVEC_EXT2_U2_SHFT 0

/* =====================================================================================

  ---M2M_TXVEC_EXT3_U2 (0x83000000 + 0x1060)---

    TXVEC_EXT3_U2[31..0]         - (RO) TX Vector EXT3 (U2)

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_TXVEC_EXT3_U2_TXVEC_EXT3_U2_ADDR WF_M2M_PHY_TOP_11AX_M2M_TXVEC_EXT3_U2_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_TXVEC_EXT3_U2_TXVEC_EXT3_U2_MASK 0xFFFFFFFF                // TXVEC_EXT3_U2[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_TXVEC_EXT3_U2_TXVEC_EXT3_U2_SHFT 0

/* =====================================================================================

  ---M2M_TXVEC_EXT1_U3 (0x83000000 + 0x1064)---

    TXVEC_EXT1_U3[31..0]         - (RO) TX Vector EXT1 (U3)

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_TXVEC_EXT1_U3_TXVEC_EXT1_U3_ADDR WF_M2M_PHY_TOP_11AX_M2M_TXVEC_EXT1_U3_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_TXVEC_EXT1_U3_TXVEC_EXT1_U3_MASK 0xFFFFFFFF                // TXVEC_EXT1_U3[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_TXVEC_EXT1_U3_TXVEC_EXT1_U3_SHFT 0

/* =====================================================================================

  ---M2M_TXVEC_EXT2_U3 (0x83000000 + 0x1068)---

    TXVEC_EXT2_U3[31..0]         - (RO) TX Vector EXT2 (U3)

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_TXVEC_EXT2_U3_TXVEC_EXT2_U3_ADDR WF_M2M_PHY_TOP_11AX_M2M_TXVEC_EXT2_U3_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_TXVEC_EXT2_U3_TXVEC_EXT2_U3_MASK 0xFFFFFFFF                // TXVEC_EXT2_U3[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_TXVEC_EXT2_U3_TXVEC_EXT2_U3_SHFT 0

/* =====================================================================================

  ---M2M_TXVEC_EXT3_U3 (0x83000000 + 0x106c)---

    TXVEC_EXT3_U3[31..0]         - (RO) TX Vector EXT3 (U3)

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_TXVEC_EXT3_U3_TXVEC_EXT3_U3_ADDR WF_M2M_PHY_TOP_11AX_M2M_TXVEC_EXT3_U3_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_TXVEC_EXT3_U3_TXVEC_EXT3_U3_MASK 0xFFFFFFFF                // TXVEC_EXT3_U3[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_TXVEC_EXT3_U3_TXVEC_EXT3_U3_SHFT 0

/* =====================================================================================

  ---M2M_TX_MANUAL_MODE (0x83000000 + 0x1100)---

    U0_MANUAL_MODE_EN[0]         - (RW) Manual mode enable for u0
    RESERVED1[1]                 - (RO) Reserved bits
    U1_MANUAL_MODE_EN[2]         - (RW) Manual mode enable for u1
    RESERVED3[3]                 - (RO) Reserved bits
    U2_MANUAL_MODE_EN[4]         - (RW) Manual mode enable for u2
    RESERVED5[5]                 - (RO) Reserved bits
    U3_MANUAL_MODE_EN[6]         - (RW) Manual mode enable for u3
    TX_MANUAL_MODE_RSV[31..7]    - (RW) Reserved

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_TX_MANUAL_MODE_TX_MANUAL_MODE_RSV_ADDR WF_M2M_PHY_TOP_11AX_M2M_TX_MANUAL_MODE_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_TX_MANUAL_MODE_TX_MANUAL_MODE_RSV_MASK 0xFFFFFF80                // TX_MANUAL_MODE_RSV[31..7]
#define WF_M2M_PHY_TOP_11AX_M2M_TX_MANUAL_MODE_TX_MANUAL_MODE_RSV_SHFT 7
#define WF_M2M_PHY_TOP_11AX_M2M_TX_MANUAL_MODE_U3_MANUAL_MODE_EN_ADDR WF_M2M_PHY_TOP_11AX_M2M_TX_MANUAL_MODE_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_TX_MANUAL_MODE_U3_MANUAL_MODE_EN_MASK 0x00000040                // U3_MANUAL_MODE_EN[6]
#define WF_M2M_PHY_TOP_11AX_M2M_TX_MANUAL_MODE_U3_MANUAL_MODE_EN_SHFT 6
#define WF_M2M_PHY_TOP_11AX_M2M_TX_MANUAL_MODE_U2_MANUAL_MODE_EN_ADDR WF_M2M_PHY_TOP_11AX_M2M_TX_MANUAL_MODE_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_TX_MANUAL_MODE_U2_MANUAL_MODE_EN_MASK 0x00000010                // U2_MANUAL_MODE_EN[4]
#define WF_M2M_PHY_TOP_11AX_M2M_TX_MANUAL_MODE_U2_MANUAL_MODE_EN_SHFT 4
#define WF_M2M_PHY_TOP_11AX_M2M_TX_MANUAL_MODE_U1_MANUAL_MODE_EN_ADDR WF_M2M_PHY_TOP_11AX_M2M_TX_MANUAL_MODE_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_TX_MANUAL_MODE_U1_MANUAL_MODE_EN_MASK 0x00000004                // U1_MANUAL_MODE_EN[2]
#define WF_M2M_PHY_TOP_11AX_M2M_TX_MANUAL_MODE_U1_MANUAL_MODE_EN_SHFT 2
#define WF_M2M_PHY_TOP_11AX_M2M_TX_MANUAL_MODE_U0_MANUAL_MODE_EN_ADDR WF_M2M_PHY_TOP_11AX_M2M_TX_MANUAL_MODE_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_TX_MANUAL_MODE_U0_MANUAL_MODE_EN_MASK 0x00000001                // U0_MANUAL_MODE_EN[0]
#define WF_M2M_PHY_TOP_11AX_M2M_TX_MANUAL_MODE_U0_MANUAL_MODE_EN_SHFT 0

/* =====================================================================================

  ---M2M_U0_TX_DATA (0x83000000 + 0x1110)---

    U0_MANUAL_MODE_DATA[31..0]   - (RW) Manual mode value for u0. When manual mode enable for u0 is 1, bit[21:0] are value of u0_m2m_tx_bus[21:0]

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_U0_TX_DATA_U0_MANUAL_MODE_DATA_ADDR WF_M2M_PHY_TOP_11AX_M2M_U0_TX_DATA_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_U0_TX_DATA_U0_MANUAL_MODE_DATA_MASK 0xFFFFFFFF                // U0_MANUAL_MODE_DATA[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_U0_TX_DATA_U0_MANUAL_MODE_DATA_SHFT 0

/* =====================================================================================

  ---M2M_U1_TX_DATA (0x83000000 + 0x1114)---

    U1_MANUAL_MODE_DATA[31..0]   - (RW) Manual mode value for u1. When manual mode enable for u1 is 1, bit[21:0] are value of u1_m2m_tx_bus[21:0]

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_U1_TX_DATA_U1_MANUAL_MODE_DATA_ADDR WF_M2M_PHY_TOP_11AX_M2M_U1_TX_DATA_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_U1_TX_DATA_U1_MANUAL_MODE_DATA_MASK 0xFFFFFFFF                // U1_MANUAL_MODE_DATA[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_U1_TX_DATA_U1_MANUAL_MODE_DATA_SHFT 0

/* =====================================================================================

  ---M2M_U2_TX_DATA (0x83000000 + 0x1118)---

    U2_MANUAL_MODE_DATA[31..0]   - (RW) Manual mode value for u2. When manual mode enable for u2 is 1, bit[21:0] are value of u2_m2m_tx_bus[21:0]

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_U2_TX_DATA_U2_MANUAL_MODE_DATA_ADDR WF_M2M_PHY_TOP_11AX_M2M_U2_TX_DATA_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_U2_TX_DATA_U2_MANUAL_MODE_DATA_MASK 0xFFFFFFFF                // U2_MANUAL_MODE_DATA[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_U2_TX_DATA_U2_MANUAL_MODE_DATA_SHFT 0

/* =====================================================================================

  ---M2M_U3_TX_DATA (0x83000000 + 0x111c)---

    U3_MANUAL_MODE_DATA[31..0]   - (RW) Manual mode value for u3. When manual mode enable for u3 is 1, bit[21:0] are value of u3_m2m_tx_bus[21:0]

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_U3_TX_DATA_U3_MANUAL_MODE_DATA_ADDR WF_M2M_PHY_TOP_11AX_M2M_U3_TX_DATA_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_U3_TX_DATA_U3_MANUAL_MODE_DATA_MASK 0xFFFFFFFF                // U3_MANUAL_MODE_DATA[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_U3_TX_DATA_U3_MANUAL_MODE_DATA_SHFT 0

/* =====================================================================================

  ---M2M_U0_RX_DATA (0x83000000 + 0x1150)---

    U0_M2MIF_RX_IN_BUS[31..0]    - (RW) bit[22:0] are value of u0_m2m_rx_bus[21:0]

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_U0_RX_DATA_U0_M2MIF_RX_IN_BUS_ADDR WF_M2M_PHY_TOP_11AX_M2M_U0_RX_DATA_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_U0_RX_DATA_U0_M2MIF_RX_IN_BUS_MASK 0xFFFFFFFF                // U0_M2MIF_RX_IN_BUS[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_U0_RX_DATA_U0_M2MIF_RX_IN_BUS_SHFT 0

/* =====================================================================================

  ---M2M_U1_RX_DATA (0x83000000 + 0x1154)---

    U1_M2MIF_RX_IN_BUS[31..0]    - (RW) bit[22:0] are value of u1_m2m_rx_bus[21:0]

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_U1_RX_DATA_U1_M2MIF_RX_IN_BUS_ADDR WF_M2M_PHY_TOP_11AX_M2M_U1_RX_DATA_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_U1_RX_DATA_U1_M2MIF_RX_IN_BUS_MASK 0xFFFFFFFF                // U1_M2MIF_RX_IN_BUS[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_U1_RX_DATA_U1_M2MIF_RX_IN_BUS_SHFT 0

/* =====================================================================================

  ---M2M_U2_RX_DATA (0x83000000 + 0x1158)---

    U2_M2MIF_RX_IN_BUS[31..0]    - (RW) bit[22:0] are value of u2_m2m_rx_bus[21:0]

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_U2_RX_DATA_U2_M2MIF_RX_IN_BUS_ADDR WF_M2M_PHY_TOP_11AX_M2M_U2_RX_DATA_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_U2_RX_DATA_U2_M2MIF_RX_IN_BUS_MASK 0xFFFFFFFF                // U2_M2MIF_RX_IN_BUS[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_U2_RX_DATA_U2_M2MIF_RX_IN_BUS_SHFT 0

/* =====================================================================================

  ---M2M_U3_RX_DATA (0x83000000 + 0x115c)---

    U3_M2MIF_RX_IN_BUS[31..0]    - (RW) bit[22:0] are value of u3_m2m_rx_bus[21:0]

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_U3_RX_DATA_U3_M2MIF_RX_IN_BUS_ADDR WF_M2M_PHY_TOP_11AX_M2M_U3_RX_DATA_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_U3_RX_DATA_U3_M2MIF_RX_IN_BUS_MASK 0xFFFFFFFF                // U3_M2MIF_RX_IN_BUS[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_U3_RX_DATA_U3_M2MIF_RX_IN_BUS_SHFT 0

/* =====================================================================================

  ---M2M_STAID_0 (0x83000000 + 0x1200)---

    STA_0_AID[10..0]             - (RW) DL MU STA_0's  AID
    STA_0_1_ID_RSV_0[15..11]     - (RW) Reserved
    STA_1_AID[26..16]            - (RW) DL MU STA_1's  AID
    STA_0_1_ID_RSV_1[31..27]     - (RW) Reserved

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_STAID_0_STA_0_1_ID_RSV_1_ADDR  WF_M2M_PHY_TOP_11AX_M2M_STAID_0_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_STAID_0_STA_0_1_ID_RSV_1_MASK  0xF8000000                // STA_0_1_ID_RSV_1[31..27]
#define WF_M2M_PHY_TOP_11AX_M2M_STAID_0_STA_0_1_ID_RSV_1_SHFT  27
#define WF_M2M_PHY_TOP_11AX_M2M_STAID_0_STA_1_AID_ADDR         WF_M2M_PHY_TOP_11AX_M2M_STAID_0_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_STAID_0_STA_1_AID_MASK         0x07FF0000                // STA_1_AID[26..16]
#define WF_M2M_PHY_TOP_11AX_M2M_STAID_0_STA_1_AID_SHFT         16
#define WF_M2M_PHY_TOP_11AX_M2M_STAID_0_STA_0_1_ID_RSV_0_ADDR  WF_M2M_PHY_TOP_11AX_M2M_STAID_0_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_STAID_0_STA_0_1_ID_RSV_0_MASK  0x0000F800                // STA_0_1_ID_RSV_0[15..11]
#define WF_M2M_PHY_TOP_11AX_M2M_STAID_0_STA_0_1_ID_RSV_0_SHFT  11
#define WF_M2M_PHY_TOP_11AX_M2M_STAID_0_STA_0_AID_ADDR         WF_M2M_PHY_TOP_11AX_M2M_STAID_0_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_STAID_0_STA_0_AID_MASK         0x000007FF                // STA_0_AID[10..0]
#define WF_M2M_PHY_TOP_11AX_M2M_STAID_0_STA_0_AID_SHFT         0

/* =====================================================================================

  ---M2M_STAID_1 (0x83000000 + 0x1204)---

    STA_2_AID[10..0]             - (RW) DL MU STA_2's  AID
    STA_2_3_ID_RSV_0[15..11]     - (RW) Reserved
    STA_3_AID[26..16]            - (RW) DL MU STA_3's  AID
    STA_2_3_ID_RSV_1[31..27]     - (RW) Reserved

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_STAID_1_STA_2_3_ID_RSV_1_ADDR  WF_M2M_PHY_TOP_11AX_M2M_STAID_1_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_STAID_1_STA_2_3_ID_RSV_1_MASK  0xF8000000                // STA_2_3_ID_RSV_1[31..27]
#define WF_M2M_PHY_TOP_11AX_M2M_STAID_1_STA_2_3_ID_RSV_1_SHFT  27
#define WF_M2M_PHY_TOP_11AX_M2M_STAID_1_STA_3_AID_ADDR         WF_M2M_PHY_TOP_11AX_M2M_STAID_1_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_STAID_1_STA_3_AID_MASK         0x07FF0000                // STA_3_AID[26..16]
#define WF_M2M_PHY_TOP_11AX_M2M_STAID_1_STA_3_AID_SHFT         16
#define WF_M2M_PHY_TOP_11AX_M2M_STAID_1_STA_2_3_ID_RSV_0_ADDR  WF_M2M_PHY_TOP_11AX_M2M_STAID_1_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_STAID_1_STA_2_3_ID_RSV_0_MASK  0x0000F800                // STA_2_3_ID_RSV_0[15..11]
#define WF_M2M_PHY_TOP_11AX_M2M_STAID_1_STA_2_3_ID_RSV_0_SHFT  11
#define WF_M2M_PHY_TOP_11AX_M2M_STAID_1_STA_2_AID_ADDR         WF_M2M_PHY_TOP_11AX_M2M_STAID_1_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_STAID_1_STA_2_AID_MASK         0x000007FF                // STA_2_AID[10..0]
#define WF_M2M_PHY_TOP_11AX_M2M_STAID_1_STA_2_AID_SHFT         0

/* =====================================================================================

  ---M2M_LENGTH_CHK0 (0x83000000 + 0x1300)---

    LENGTH_CHK_0_LENGTH[11..0]   - (RO) TX length once TX length check fails
    LENGTH_CHK_0_RSV1[15..12]    - (RO) Reserved
    LENGTH_CHK_0_PFD[19..16]     - (RO) PFD value once TX length check fails
    LENGTH_CHK_0_RSV2[30..20]    - (RO) Reserved
    LENGTH_CHK_0_FAIL[31]        - (RO) TX length check fail for HE_SU and HE_TB type

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_LENGTH_CHK0_LENGTH_CHK_0_FAIL_ADDR WF_M2M_PHY_TOP_11AX_M2M_LENGTH_CHK0_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_LENGTH_CHK0_LENGTH_CHK_0_FAIL_MASK 0x80000000                // LENGTH_CHK_0_FAIL[31]
#define WF_M2M_PHY_TOP_11AX_M2M_LENGTH_CHK0_LENGTH_CHK_0_FAIL_SHFT 31
#define WF_M2M_PHY_TOP_11AX_M2M_LENGTH_CHK0_LENGTH_CHK_0_RSV2_ADDR WF_M2M_PHY_TOP_11AX_M2M_LENGTH_CHK0_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_LENGTH_CHK0_LENGTH_CHK_0_RSV2_MASK 0x7FF00000                // LENGTH_CHK_0_RSV2[30..20]
#define WF_M2M_PHY_TOP_11AX_M2M_LENGTH_CHK0_LENGTH_CHK_0_RSV2_SHFT 20
#define WF_M2M_PHY_TOP_11AX_M2M_LENGTH_CHK0_LENGTH_CHK_0_PFD_ADDR WF_M2M_PHY_TOP_11AX_M2M_LENGTH_CHK0_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_LENGTH_CHK0_LENGTH_CHK_0_PFD_MASK 0x000F0000                // LENGTH_CHK_0_PFD[19..16]
#define WF_M2M_PHY_TOP_11AX_M2M_LENGTH_CHK0_LENGTH_CHK_0_PFD_SHFT 16
#define WF_M2M_PHY_TOP_11AX_M2M_LENGTH_CHK0_LENGTH_CHK_0_RSV1_ADDR WF_M2M_PHY_TOP_11AX_M2M_LENGTH_CHK0_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_LENGTH_CHK0_LENGTH_CHK_0_RSV1_MASK 0x0000F000                // LENGTH_CHK_0_RSV1[15..12]
#define WF_M2M_PHY_TOP_11AX_M2M_LENGTH_CHK0_LENGTH_CHK_0_RSV1_SHFT 12
#define WF_M2M_PHY_TOP_11AX_M2M_LENGTH_CHK0_LENGTH_CHK_0_LENGTH_ADDR WF_M2M_PHY_TOP_11AX_M2M_LENGTH_CHK0_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_LENGTH_CHK0_LENGTH_CHK_0_LENGTH_MASK 0x00000FFF                // LENGTH_CHK_0_LENGTH[11..0]
#define WF_M2M_PHY_TOP_11AX_M2M_LENGTH_CHK0_LENGTH_CHK_0_LENGTH_SHFT 0

/* =====================================================================================

  ---M2M_LENGTH_CHK1 (0x83000000 + 0x1304)---

    LENGTH_CHK_1_LENGTH[11..0]   - (RO) TX length once TX length check fails
    LENGTH_CHK_1_RSV1[15..12]    - (RO) Reserved
    LENGTH_CHK_1_PFD[19..16]     - (RO) PFD value once TX length check fails
    LENGTH_CHK_1_RSV2[30..20]    - (RO) Reserved
    LENGTH_CHK_1_FAIL[31]        - (RO) TX length check fail for HE_EXT_SU and HE_MU type

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_LENGTH_CHK1_LENGTH_CHK_1_FAIL_ADDR WF_M2M_PHY_TOP_11AX_M2M_LENGTH_CHK1_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_LENGTH_CHK1_LENGTH_CHK_1_FAIL_MASK 0x80000000                // LENGTH_CHK_1_FAIL[31]
#define WF_M2M_PHY_TOP_11AX_M2M_LENGTH_CHK1_LENGTH_CHK_1_FAIL_SHFT 31
#define WF_M2M_PHY_TOP_11AX_M2M_LENGTH_CHK1_LENGTH_CHK_1_RSV2_ADDR WF_M2M_PHY_TOP_11AX_M2M_LENGTH_CHK1_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_LENGTH_CHK1_LENGTH_CHK_1_RSV2_MASK 0x7FF00000                // LENGTH_CHK_1_RSV2[30..20]
#define WF_M2M_PHY_TOP_11AX_M2M_LENGTH_CHK1_LENGTH_CHK_1_RSV2_SHFT 20
#define WF_M2M_PHY_TOP_11AX_M2M_LENGTH_CHK1_LENGTH_CHK_1_PFD_ADDR WF_M2M_PHY_TOP_11AX_M2M_LENGTH_CHK1_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_LENGTH_CHK1_LENGTH_CHK_1_PFD_MASK 0x000F0000                // LENGTH_CHK_1_PFD[19..16]
#define WF_M2M_PHY_TOP_11AX_M2M_LENGTH_CHK1_LENGTH_CHK_1_PFD_SHFT 16
#define WF_M2M_PHY_TOP_11AX_M2M_LENGTH_CHK1_LENGTH_CHK_1_RSV1_ADDR WF_M2M_PHY_TOP_11AX_M2M_LENGTH_CHK1_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_LENGTH_CHK1_LENGTH_CHK_1_RSV1_MASK 0x0000F000                // LENGTH_CHK_1_RSV1[15..12]
#define WF_M2M_PHY_TOP_11AX_M2M_LENGTH_CHK1_LENGTH_CHK_1_RSV1_SHFT 12
#define WF_M2M_PHY_TOP_11AX_M2M_LENGTH_CHK1_LENGTH_CHK_1_LENGTH_ADDR WF_M2M_PHY_TOP_11AX_M2M_LENGTH_CHK1_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_LENGTH_CHK1_LENGTH_CHK_1_LENGTH_MASK 0x00000FFF                // LENGTH_CHK_1_LENGTH[11..0]
#define WF_M2M_PHY_TOP_11AX_M2M_LENGTH_CHK1_LENGTH_CHK_1_LENGTH_SHFT 0

/* =====================================================================================

  ---M2M_RXVEC_EXT1_U0 (0x83000000 + 0x2010)---

    RXVEC_EXT1[31..0]            - (RO) RX Vector EXT1 (U0)

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC_EXT1_U0_RXVEC_EXT1_ADDR  WF_M2M_PHY_TOP_11AX_M2M_RXVEC_EXT1_U0_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC_EXT1_U0_RXVEC_EXT1_MASK  0xFFFFFFFF                // RXVEC_EXT1[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC_EXT1_U0_RXVEC_EXT1_SHFT  0

/* =====================================================================================

  ---M2M_RXVEC_EXT2_U0 (0x83000000 + 0x2014)---

    RXVEC_EXT2[31..0]            - (RO) RX Vector EXT2 (U0)

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC_EXT2_U0_RXVEC_EXT2_ADDR  WF_M2M_PHY_TOP_11AX_M2M_RXVEC_EXT2_U0_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC_EXT2_U0_RXVEC_EXT2_MASK  0xFFFFFFFF                // RXVEC_EXT2[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC_EXT2_U0_RXVEC_EXT2_SHFT  0

/* =====================================================================================

  ---M2M_RXVEC_EXT3_U0 (0x83000000 + 0x2018)---

    RXVEC_EXT3[31..0]            - (RO) RX Vector EXT3 (U0)

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC_EXT3_U0_RXVEC_EXT3_ADDR  WF_M2M_PHY_TOP_11AX_M2M_RXVEC_EXT3_U0_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC_EXT3_U0_RXVEC_EXT3_MASK  0xFFFFFFFF                // RXVEC_EXT3[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC_EXT3_U0_RXVEC_EXT3_SHFT  0

/* =====================================================================================

  ---M2M_RXVEC_EXT1_U1 (0x83000000 + 0x201c)---

    RXVEC_EXT1[31..0]            - (RO) RX Vector EXT1 (U1)

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC_EXT1_U1_RXVEC_EXT1_ADDR  WF_M2M_PHY_TOP_11AX_M2M_RXVEC_EXT1_U1_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC_EXT1_U1_RXVEC_EXT1_MASK  0xFFFFFFFF                // RXVEC_EXT1[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC_EXT1_U1_RXVEC_EXT1_SHFT  0

/* =====================================================================================

  ---M2M_RXVEC_EXT2_U1 (0x83000000 + 0x2020)---

    RXVEC_EXT2[31..0]            - (RO) RX Vector EXT2 (U1)

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC_EXT2_U1_RXVEC_EXT2_ADDR  WF_M2M_PHY_TOP_11AX_M2M_RXVEC_EXT2_U1_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC_EXT2_U1_RXVEC_EXT2_MASK  0xFFFFFFFF                // RXVEC_EXT2[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC_EXT2_U1_RXVEC_EXT2_SHFT  0

/* =====================================================================================

  ---M2M_RXVEC_EXT3_U1 (0x83000000 + 0x2024)---

    RXVEC_EXT3[31..0]            - (RO) RX Vector EXT3 (U1)

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC_EXT3_U1_RXVEC_EXT3_ADDR  WF_M2M_PHY_TOP_11AX_M2M_RXVEC_EXT3_U1_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC_EXT3_U1_RXVEC_EXT3_MASK  0xFFFFFFFF                // RXVEC_EXT3[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC_EXT3_U1_RXVEC_EXT3_SHFT  0

/* =====================================================================================

  ---M2M_RXVEC_EXT1_U2 (0x83000000 + 0x2028)---

    RXVEC_EXT1[31..0]            - (RO) RX Vector EXT1 (U2)

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC_EXT1_U2_RXVEC_EXT1_ADDR  WF_M2M_PHY_TOP_11AX_M2M_RXVEC_EXT1_U2_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC_EXT1_U2_RXVEC_EXT1_MASK  0xFFFFFFFF                // RXVEC_EXT1[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC_EXT1_U2_RXVEC_EXT1_SHFT  0

/* =====================================================================================

  ---M2M_RXVEC_EXT2_U2 (0x83000000 + 0x202c)---

    RXVEC_EXT2[31..0]            - (RO) RX Vector EXT2 (U2)

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC_EXT2_U2_RXVEC_EXT2_ADDR  WF_M2M_PHY_TOP_11AX_M2M_RXVEC_EXT2_U2_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC_EXT2_U2_RXVEC_EXT2_MASK  0xFFFFFFFF                // RXVEC_EXT2[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC_EXT2_U2_RXVEC_EXT2_SHFT  0

/* =====================================================================================

  ---M2M_RXVEC_EXT3_U2 (0x83000000 + 0x2030)---

    RXVEC_EXT3[31..0]            - (RO) RX Vector EXT3 (U2)

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC_EXT3_U2_RXVEC_EXT3_ADDR  WF_M2M_PHY_TOP_11AX_M2M_RXVEC_EXT3_U2_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC_EXT3_U2_RXVEC_EXT3_MASK  0xFFFFFFFF                // RXVEC_EXT3[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC_EXT3_U2_RXVEC_EXT3_SHFT  0

/* =====================================================================================

  ---M2M_RXVEC_EXT1_U3 (0x83000000 + 0x2034)---

    RXVEC_EXT1[31..0]            - (RO) RX Vector EXT1 (U3)

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC_EXT1_U3_RXVEC_EXT1_ADDR  WF_M2M_PHY_TOP_11AX_M2M_RXVEC_EXT1_U3_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC_EXT1_U3_RXVEC_EXT1_MASK  0xFFFFFFFF                // RXVEC_EXT1[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC_EXT1_U3_RXVEC_EXT1_SHFT  0

/* =====================================================================================

  ---M2M_RXVEC_EXT2_U3 (0x83000000 + 0x2038)---

    RXVEC_EXT2[31..0]            - (RO) RX Vector EXT2 (U3)

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC_EXT2_U3_RXVEC_EXT2_ADDR  WF_M2M_PHY_TOP_11AX_M2M_RXVEC_EXT2_U3_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC_EXT2_U3_RXVEC_EXT2_MASK  0xFFFFFFFF                // RXVEC_EXT2[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC_EXT2_U3_RXVEC_EXT2_SHFT  0

/* =====================================================================================

  ---M2M_RXVEC_EXT3_U3 (0x83000000 + 0x203c)---

    RXVEC_EXT3[31..0]            - (RO) RX Vector EXT3 (U3)

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC_EXT3_U3_RXVEC_EXT3_ADDR  WF_M2M_PHY_TOP_11AX_M2M_RXVEC_EXT3_U3_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC_EXT3_U3_RXVEC_EXT3_MASK  0xFFFFFFFF                // RXVEC_EXT3[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXVEC_EXT3_U3_RXVEC_EXT3_SHFT  0

/* =====================================================================================

  ---M2M_RX_CTRL (0x83000000 + 0x2100)---

    RXV_RSSI_CTRL[0]             - (RW) 1: Per user RSSI is control by CR.
                                     0: Per user RSSI is control by channel model.
    RXV_LQ_SNR_CTRL[1]           - (RW) 1: LQ SNR is control by CR.
                                     0: LQ SNR is control by channel model.
    RX_CTRL_RSV[23..2]           - (RW) Reserved
    RX_FIFO_CHECK[24]            - (RW) 1: If FIFO isn't empty, RX MDRDY keeps high.
                                     0: RX MDRDY will be low by timeout even FIFO isn't empty.
    RX_CTRL_RSV_2[31..25]        - (RW) Reserved

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RX_CTRL_RX_CTRL_RSV_2_ADDR     WF_M2M_PHY_TOP_11AX_M2M_RX_CTRL_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RX_CTRL_RX_CTRL_RSV_2_MASK     0xFE000000                // RX_CTRL_RSV_2[31..25]
#define WF_M2M_PHY_TOP_11AX_M2M_RX_CTRL_RX_CTRL_RSV_2_SHFT     25
#define WF_M2M_PHY_TOP_11AX_M2M_RX_CTRL_RX_FIFO_CHECK_ADDR     WF_M2M_PHY_TOP_11AX_M2M_RX_CTRL_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RX_CTRL_RX_FIFO_CHECK_MASK     0x01000000                // RX_FIFO_CHECK[24]
#define WF_M2M_PHY_TOP_11AX_M2M_RX_CTRL_RX_FIFO_CHECK_SHFT     24
#define WF_M2M_PHY_TOP_11AX_M2M_RX_CTRL_RX_CTRL_RSV_ADDR       WF_M2M_PHY_TOP_11AX_M2M_RX_CTRL_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RX_CTRL_RX_CTRL_RSV_MASK       0x00FFFFFC                // RX_CTRL_RSV[23..2]
#define WF_M2M_PHY_TOP_11AX_M2M_RX_CTRL_RX_CTRL_RSV_SHFT       2
#define WF_M2M_PHY_TOP_11AX_M2M_RX_CTRL_RXV_LQ_SNR_CTRL_ADDR   WF_M2M_PHY_TOP_11AX_M2M_RX_CTRL_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RX_CTRL_RXV_LQ_SNR_CTRL_MASK   0x00000002                // RXV_LQ_SNR_CTRL[1]
#define WF_M2M_PHY_TOP_11AX_M2M_RX_CTRL_RXV_LQ_SNR_CTRL_SHFT   1
#define WF_M2M_PHY_TOP_11AX_M2M_RX_CTRL_RXV_RSSI_CTRL_ADDR     WF_M2M_PHY_TOP_11AX_M2M_RX_CTRL_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RX_CTRL_RXV_RSSI_CTRL_MASK     0x00000001                // RXV_RSSI_CTRL[0]
#define WF_M2M_PHY_TOP_11AX_M2M_RX_CTRL_RXV_RSSI_CTRL_SHFT     0

/* =====================================================================================

  ---M2M_RXV_CB0_DW0 (0x83000000 + 0x2110)---

    RXV_CB0_DW0[31..0]           - (RW) The value of RXV CB0 DW0. Bit 19, 21 and 22 are from this CR. Others are from TXV.

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CB0_DW0_RXV_CB0_DW0_ADDR   WF_M2M_PHY_TOP_11AX_M2M_RXV_CB0_DW0_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CB0_DW0_RXV_CB0_DW0_MASK   0xFFFFFFFF                // RXV_CB0_DW0[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CB0_DW0_RXV_CB0_DW0_SHFT   0

/* =====================================================================================

  ---M2M_RXV_CB1_DW0 (0x83000000 + 0x2118)---

    RXV_CB1_DW0[31..0]           - (RW) The value of RXV CB1 DW0. Bit0~21 and 31 are from this CR. Others are from TXV.

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CB1_DW0_RXV_CB1_DW0_ADDR   WF_M2M_PHY_TOP_11AX_M2M_RXV_CB1_DW0_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CB1_DW0_RXV_CB1_DW0_MASK   0xFFFFFFFF                // RXV_CB1_DW0[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CB1_DW0_RXV_CB1_DW0_SHFT   0

/* =====================================================================================

  ---M2M_RXV_CB2_DW0 (0x83000000 + 0x2120)---

    RXV_CB2_DW0[31..0]           - (RW) The value of RXV CB2 DW0.

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CB2_DW0_RXV_CB2_DW0_ADDR   WF_M2M_PHY_TOP_11AX_M2M_RXV_CB2_DW0_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CB2_DW0_RXV_CB2_DW0_MASK   0xFFFFFFFF                // RXV_CB2_DW0[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CB2_DW0_RXV_CB2_DW0_SHFT   0

/* =====================================================================================

  ---M2M_RXV_CB2_DW1 (0x83000000 + 0x2124)---

    RXV_CB2_DW1[31..0]           - (RW) The value of RXV CB2 DW1. Bit0~19 and Bit31 are from this CR. Others are from TXV.

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CB2_DW1_RXV_CB2_DW1_ADDR   WF_M2M_PHY_TOP_11AX_M2M_RXV_CB2_DW1_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CB2_DW1_RXV_CB2_DW1_MASK   0xFFFFFFFF                // RXV_CB2_DW1[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CB2_DW1_RXV_CB2_DW1_SHFT   0

/* =====================================================================================

  ---M2M_RXV_CB3_DW0 (0x83000000 + 0x2128)---

    RXV_CB3_DW0[31..0]           - (RW) The value of RXV CB3 DW0.

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CB3_DW0_RXV_CB3_DW0_ADDR   WF_M2M_PHY_TOP_11AX_M2M_RXV_CB3_DW0_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CB3_DW0_RXV_CB3_DW0_MASK   0xFFFFFFFF                // RXV_CB3_DW0[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CB3_DW0_RXV_CB3_DW0_SHFT   0

/* =====================================================================================

  ---M2M_RXV_CB3_DW1 (0x83000000 + 0x212C)---

    RXV_CB3_DW1[31..0]           - (RW) The value of RXV CB3 DW1.

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CB3_DW1_RXV_CB3_DW1_ADDR   WF_M2M_PHY_TOP_11AX_M2M_RXV_CB3_DW1_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CB3_DW1_RXV_CB3_DW1_MASK   0xFFFFFFFF                // RXV_CB3_DW1[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CB3_DW1_RXV_CB3_DW1_SHFT   0

/* =====================================================================================

  ---M2M_RXV_CB4_DW0 (0x83000000 + 0x2130)---

    RXV_CB4_DW0[31..0]           - (RW) The value of RXV CB4 DW0.

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CB4_DW0_RXV_CB4_DW0_ADDR   WF_M2M_PHY_TOP_11AX_M2M_RXV_CB4_DW0_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CB4_DW0_RXV_CB4_DW0_MASK   0xFFFFFFFF                // RXV_CB4_DW0[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CB4_DW0_RXV_CB4_DW0_SHFT   0

/* =====================================================================================

  ---M2M_RXV_CB4_DW1 (0x83000000 + 0x2134)---

    RXV_CB4_DW1[31..0]           - (RW) The value of RXV CB4 DW1. Bit 31~24 are from this CR. Others are from TXV.

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CB4_DW1_RXV_CB4_DW1_ADDR   WF_M2M_PHY_TOP_11AX_M2M_RXV_CB4_DW1_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CB4_DW1_RXV_CB4_DW1_MASK   0xFFFFFFFF                // RXV_CB4_DW1[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CB4_DW1_RXV_CB4_DW1_SHFT   0

/* =====================================================================================

  ---M2M_RXV_CB5_DW0 (0x83000000 + 0x2138)---

    RXV_CB5_DW0[31..0]           - (RW) The value of RXV CB5 DW0.

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CB5_DW0_RXV_CB5_DW0_ADDR   WF_M2M_PHY_TOP_11AX_M2M_RXV_CB5_DW0_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CB5_DW0_RXV_CB5_DW0_MASK   0xFFFFFFFF                // RXV_CB5_DW0[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CB5_DW0_RXV_CB5_DW0_SHFT   0

/* =====================================================================================

  ---M2M_RXV_CB5_DW1 (0x83000000 + 0x213C)---

    RXV_CB5_DW1[31..0]           - (RW) The value of RXV CB5 DW1.

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CB5_DW1_RXV_CB5_DW1_ADDR   WF_M2M_PHY_TOP_11AX_M2M_RXV_CB5_DW1_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CB5_DW1_RXV_CB5_DW1_MASK   0xFFFFFFFF                // RXV_CB5_DW1[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CB5_DW1_RXV_CB5_DW1_SHFT   0

/* =====================================================================================

  ---M2M_RXV_CB6_DW0 (0x83000000 + 0x2140)---

    RXV_CB6_DW0[31..0]           - (RW) The value of RXV CB6 DW0. Bit 31~16 are from this CR. Others are from TXV.

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CB6_DW0_RXV_CB6_DW0_ADDR   WF_M2M_PHY_TOP_11AX_M2M_RXV_CB6_DW0_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CB6_DW0_RXV_CB6_DW0_MASK   0xFFFFFFFF                // RXV_CB6_DW0[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CB6_DW0_RXV_CB6_DW0_SHFT   0

/* =====================================================================================

  ---M2M_RXV_CB6_DW1 (0x83000000 + 0x2144)---

    RXV_CB6_DW1[31..0]           - (RW) The value of RXV CB6 DW1.

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CB6_DW1_RXV_CB6_DW1_ADDR   WF_M2M_PHY_TOP_11AX_M2M_RXV_CB6_DW1_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CB6_DW1_RXV_CB6_DW1_MASK   0xFFFFFFFF                // RXV_CB6_DW1[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CB6_DW1_RXV_CB6_DW1_SHFT   0

/* =====================================================================================

  ---M2M_RXV_CB7_DW0 (0x83000000 + 0x2148)---

    RXV_CB7_DW0[31..0]           - (RW) The value of RXV CB7 DW0.

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CB7_DW0_RXV_CB7_DW0_ADDR   WF_M2M_PHY_TOP_11AX_M2M_RXV_CB7_DW0_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CB7_DW0_RXV_CB7_DW0_MASK   0xFFFFFFFF                // RXV_CB7_DW0[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CB7_DW0_RXV_CB7_DW0_SHFT   0

/* =====================================================================================

  ---M2M_RXV_CB7_DW1 (0x83000000 + 0x214C)---

    RXV_CB7_DW1[31..0]           - (RW) The value of RXV CB7 DW1.

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CB7_DW1_RXV_CB7_DW1_ADDR   WF_M2M_PHY_TOP_11AX_M2M_RXV_CB7_DW1_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CB7_DW1_RXV_CB7_DW1_MASK   0xFFFFFFFF                // RXV_CB7_DW1[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CB7_DW1_RXV_CB7_DW1_SHFT   0

/* =====================================================================================

  ---M2M_RXV_CB8_DW0 (0x83000000 + 0x2150)---

    RXV_CB8_DW0[31..0]           - (RW) The value of RXV CB8 DW0.

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CB8_DW0_RXV_CB8_DW0_ADDR   WF_M2M_PHY_TOP_11AX_M2M_RXV_CB8_DW0_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CB8_DW0_RXV_CB8_DW0_MASK   0xFFFFFFFF                // RXV_CB8_DW0[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CB8_DW0_RXV_CB8_DW0_SHFT   0

/* =====================================================================================

  ---M2M_RXV_CB8_DW1 (0x83000000 + 0x2154)---

    RXV_CB8_DW1[31..0]           - (RW) The value of RXV CB8 DW1.

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CB8_DW1_RXV_CB8_DW1_ADDR   WF_M2M_PHY_TOP_11AX_M2M_RXV_CB8_DW1_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CB8_DW1_RXV_CB8_DW1_MASK   0xFFFFFFFF                // RXV_CB8_DW1[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CB8_DW1_RXV_CB8_DW1_SHFT   0

/* =====================================================================================

  ---M2M_RXV_PB0_DW0 (0x83000000 + 0x2200)---

    RXV_PB0_DW0[31..0]           - (RW) The value of RXV PB0 DW0. Bit 10, and 27~22 are from this CR. Others are from TXV.

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_PB0_DW0_RXV_PB0_DW0_ADDR   WF_M2M_PHY_TOP_11AX_M2M_RXV_PB0_DW0_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_PB0_DW0_RXV_PB0_DW0_MASK   0xFFFFFFFF                // RXV_PB0_DW0[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_PB0_DW0_RXV_PB0_DW0_SHFT   0

/* =====================================================================================

  ---M2M_RXV_PB0_DW1 (0x83000000 + 0x2204)---

    RXV_PB0_DW1[31..0]           - (RW) The value of RXV PB0 DW1. Bit 7~4 and 30 are from this CR. Others are from TXV.

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_PB0_DW1_RXV_PB0_DW1_ADDR   WF_M2M_PHY_TOP_11AX_M2M_RXV_PB0_DW1_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_PB0_DW1_RXV_PB0_DW1_MASK   0xFFFFFFFF                // RXV_PB0_DW1[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_PB0_DW1_RXV_PB0_DW1_SHFT   0

/* =====================================================================================

  ---M2M_RXV_PA0_DW0 (0x83000000 + 0x2280)---

    RXV_PA0_DW0[31..0]           - (RW) The value of RXV PA0 DW0. Bit 31~1 are from this CR. Others are from TXV.

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_PA0_DW0_RXV_PA0_DW0_ADDR   WF_M2M_PHY_TOP_11AX_M2M_RXV_PA0_DW0_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_PA0_DW0_RXV_PA0_DW0_MASK   0xFFFFFFFF                // RXV_PA0_DW0[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_PA0_DW0_RXV_PA0_DW0_SHFT   0

/* =====================================================================================

  ---M2M_RXV_PA0_DW1 (0x83000000 + 0x2284)---

    RXV_PA0_DW1[31..0]           - (RW) The value of RXV PA0 DW1.

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_PA0_DW1_RXV_PA0_DW1_ADDR   WF_M2M_PHY_TOP_11AX_M2M_RXV_PA0_DW1_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_PA0_DW1_RXV_PA0_DW1_MASK   0xFFFFFFFF                // RXV_PA0_DW1[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_PA0_DW1_RXV_PA0_DW1_SHFT   0

/* =====================================================================================

  ---M2M_RXV_PA1_DW0 (0x83000000 + 0x2288)---

    RXV_PA1_DW0[31..0]           - (RW) The value of RXV PA1 DW0.

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_PA1_DW0_RXV_PA1_DW0_ADDR   WF_M2M_PHY_TOP_11AX_M2M_RXV_PA1_DW0_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_PA1_DW0_RXV_PA1_DW0_MASK   0xFFFFFFFF                // RXV_PA1_DW0[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_PA1_DW0_RXV_PA1_DW0_SHFT   0

/* =====================================================================================

  ---M2M_RXV_PA1_DW1 (0x83000000 + 0x228C)---

    RXV_PA1_DW1[31..0]           - (RW) The value of RXV PA1 DW1.

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_PA1_DW1_RXV_PA1_DW1_ADDR   WF_M2M_PHY_TOP_11AX_M2M_RXV_PA1_DW1_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_PA1_DW1_RXV_PA1_DW1_MASK   0xFFFFFFFF                // RXV_PA1_DW1[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_PA1_DW1_RXV_PA1_DW1_SHFT   0

/* =====================================================================================

  ---M2M_RXV_PA2_DW0 (0x83000000 + 0x2290)---

    RXV_PA2_DW0[31..0]           - (RW) The value of RXV PA2 DW0.

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_PA2_DW0_RXV_PA2_DW0_ADDR   WF_M2M_PHY_TOP_11AX_M2M_RXV_PA2_DW0_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_PA2_DW0_RXV_PA2_DW0_MASK   0xFFFFFFFF                // RXV_PA2_DW0[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_PA2_DW0_RXV_PA2_DW0_SHFT   0

/* =====================================================================================

  ---M2M_RXV_PA2_DW1 (0x83000000 + 0x2294)---

    RXV_PA2_DW1[31..0]           - (RW) The value of RXV PA2 DW1.

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_PA2_DW1_RXV_PA2_DW1_ADDR   WF_M2M_PHY_TOP_11AX_M2M_RXV_PA2_DW1_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_PA2_DW1_RXV_PA2_DW1_MASK   0xFFFFFFFF                // RXV_PA2_DW1[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_PA2_DW1_RXV_PA2_DW1_SHFT   0

/* =====================================================================================

  ---M2M_RXV_CA0_DW0 (0x83000000 + 0x2300)---

    RXV_CA0_DW0[31..0]           - (RW) The value of RXV CA0 DW0.

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA0_DW0_RXV_CA0_DW0_ADDR   WF_M2M_PHY_TOP_11AX_M2M_RXV_CA0_DW0_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA0_DW0_RXV_CA0_DW0_MASK   0xFFFFFFFF                // RXV_CA0_DW0[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA0_DW0_RXV_CA0_DW0_SHFT   0

/* =====================================================================================

  ---M2M_RXV_CA0_DW1 (0x83000000 + 0x2304)---

    RXV_CA0_DW1[31..0]           - (RW) The value of RXV CA0 DW1.

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA0_DW1_RXV_CA0_DW1_ADDR   WF_M2M_PHY_TOP_11AX_M2M_RXV_CA0_DW1_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA0_DW1_RXV_CA0_DW1_MASK   0xFFFFFFFF                // RXV_CA0_DW1[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA0_DW1_RXV_CA0_DW1_SHFT   0

/* =====================================================================================

  ---M2M_RXV_CA1_DW0 (0x83000000 + 0x2308)---

    RXV_CA1_DW0[31..0]           - (RW) The value of RXV CA1 DW0.

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA1_DW0_RXV_CA1_DW0_ADDR   WF_M2M_PHY_TOP_11AX_M2M_RXV_CA1_DW0_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA1_DW0_RXV_CA1_DW0_MASK   0xFFFFFFFF                // RXV_CA1_DW0[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA1_DW0_RXV_CA1_DW0_SHFT   0

/* =====================================================================================

  ---M2M_RXV_CA1_DW1 (0x83000000 + 0x230C)---

    RXV_CA1_DW1[31..0]           - (RW) The value of RXV CA1 DW1.

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA1_DW1_RXV_CA1_DW1_ADDR   WF_M2M_PHY_TOP_11AX_M2M_RXV_CA1_DW1_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA1_DW1_RXV_CA1_DW1_MASK   0xFFFFFFFF                // RXV_CA1_DW1[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA1_DW1_RXV_CA1_DW1_SHFT   0

/* =====================================================================================

  ---M2M_RXV_CA2_DW0 (0x83000000 + 0x2310)---

    RXV_CA2_DW0[31..0]           - (RW) The value of RXV CA2 DW0. Bit 29~0 are from this CR. Others are from TXV.

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA2_DW0_RXV_CA2_DW0_ADDR   WF_M2M_PHY_TOP_11AX_M2M_RXV_CA2_DW0_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA2_DW0_RXV_CA2_DW0_MASK   0xFFFFFFFF                // RXV_CA2_DW0[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA2_DW0_RXV_CA2_DW0_SHFT   0

/* =====================================================================================

  ---M2M_RXV_CA2_DW1 (0x83000000 + 0x2314)---

    RXV_CA2_DW1[31..0]           - (RW) The value of RXV CA2 DW1. Bit 31~2 are from this CR. Others are from TXV.

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA2_DW1_RXV_CA2_DW1_ADDR   WF_M2M_PHY_TOP_11AX_M2M_RXV_CA2_DW1_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA2_DW1_RXV_CA2_DW1_MASK   0xFFFFFFFF                // RXV_CA2_DW1[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA2_DW1_RXV_CA2_DW1_SHFT   0

/* =====================================================================================

  ---M2M_RXV_CA3_DW0 (0x83000000 + 0x2318)---

    RXV_CA3_DW0[31..0]           - (RW) The value of RXV CA3 DW0.

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA3_DW0_RXV_CA3_DW0_ADDR   WF_M2M_PHY_TOP_11AX_M2M_RXV_CA3_DW0_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA3_DW0_RXV_CA3_DW0_MASK   0xFFFFFFFF                // RXV_CA3_DW0[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA3_DW0_RXV_CA3_DW0_SHFT   0

/* =====================================================================================

  ---M2M_RXV_CA3_DW1 (0x83000000 + 0x231C)---

    RXV_CA3_DW1[31..0]           - (RW) The value of RXV CA3 DW1.

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA3_DW1_RXV_CA3_DW1_ADDR   WF_M2M_PHY_TOP_11AX_M2M_RXV_CA3_DW1_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA3_DW1_RXV_CA3_DW1_MASK   0xFFFFFFFF                // RXV_CA3_DW1[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA3_DW1_RXV_CA3_DW1_SHFT   0

/* =====================================================================================

  ---M2M_RXV_CA4_DW0 (0x83000000 + 0x2320)---

    RXV_CA4_DW0[31..0]           - (RW) The value of RXV CA4 DW0.

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA4_DW0_RXV_CA4_DW0_ADDR   WF_M2M_PHY_TOP_11AX_M2M_RXV_CA4_DW0_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA4_DW0_RXV_CA4_DW0_MASK   0xFFFFFFFF                // RXV_CA4_DW0[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA4_DW0_RXV_CA4_DW0_SHFT   0

/* =====================================================================================

  ---M2M_RXV_CA4_DW1 (0x83000000 + 0x2324)---

    RXV_CA4_DW1[31..0]           - (RW) The value of RXV CA4 DW1.

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA4_DW1_RXV_CA4_DW1_ADDR   WF_M2M_PHY_TOP_11AX_M2M_RXV_CA4_DW1_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA4_DW1_RXV_CA4_DW1_MASK   0xFFFFFFFF                // RXV_CA4_DW1[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA4_DW1_RXV_CA4_DW1_SHFT   0

/* =====================================================================================

  ---M2M_RXV_CA5_DW0 (0x83000000 + 0x2328)---

    RXV_CA5_DW0[31..0]           - (RW) The value of RXV CA5 DW0 when RXV_LQ_SNR_CTRL is 1.

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA5_DW0_RXV_CA5_DW0_ADDR   WF_M2M_PHY_TOP_11AX_M2M_RXV_CA5_DW0_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA5_DW0_RXV_CA5_DW0_MASK   0xFFFFFFFF                // RXV_CA5_DW0[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA5_DW0_RXV_CA5_DW0_SHFT   0

/* =====================================================================================

  ---M2M_RXV_CA5_DW1 (0x83000000 + 0x232C)---

    RXV_CA5_DW1[31..0]           - (RW) The value of RXV CA5 DW1 when RXV_LQ_SNR_CTRL is 1.

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA5_DW1_RXV_CA5_DW1_ADDR   WF_M2M_PHY_TOP_11AX_M2M_RXV_CA5_DW1_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA5_DW1_RXV_CA5_DW1_MASK   0xFFFFFFFF                // RXV_CA5_DW1[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA5_DW1_RXV_CA5_DW1_SHFT   0

/* =====================================================================================

  ---M2M_RXV_CA6_DW0 (0x83000000 + 0x2330)---

    RXV_CA6_DW0[31..0]           - (RW) The value of RXV CA6 DW0 when RXV_LQ_SNR_CTRL is 1.

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA6_DW0_RXV_CA6_DW0_ADDR   WF_M2M_PHY_TOP_11AX_M2M_RXV_CA6_DW0_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA6_DW0_RXV_CA6_DW0_MASK   0xFFFFFFFF                // RXV_CA6_DW0[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA6_DW0_RXV_CA6_DW0_SHFT   0

/* =====================================================================================

  ---M2M_RXV_CA6_DW1 (0x83000000 + 0x2334)---

    RXV_CA6_DW1[31..0]           - (RW) The value of RXV CA6 DW1 when RXV_LQ_SNR_CTRL is 1.

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA6_DW1_RXV_CA6_DW1_ADDR   WF_M2M_PHY_TOP_11AX_M2M_RXV_CA6_DW1_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA6_DW1_RXV_CA6_DW1_MASK   0xFFFFFFFF                // RXV_CA6_DW1[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA6_DW1_RXV_CA6_DW1_SHFT   0

/* =====================================================================================

  ---M2M_RXV_CA7_DW0 (0x83000000 + 0x2338)---

    RXV_CA7_DW0[31..0]           - (RW) The value of RXV CA7 DW0 when RXV_LQ_SNR_CTRL is 1.

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA7_DW0_RXV_CA7_DW0_ADDR   WF_M2M_PHY_TOP_11AX_M2M_RXV_CA7_DW0_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA7_DW0_RXV_CA7_DW0_MASK   0xFFFFFFFF                // RXV_CA7_DW0[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA7_DW0_RXV_CA7_DW0_SHFT   0

/* =====================================================================================

  ---M2M_RXV_CA7_DW1 (0x83000000 + 0x233C)---

    RXV_CA7_DW1[31..0]           - (RW) The value of RXV CA7 DW1 when RXV_LQ_SNR_CTRL is 1.

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA7_DW1_RXV_CA7_DW1_ADDR   WF_M2M_PHY_TOP_11AX_M2M_RXV_CA7_DW1_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA7_DW1_RXV_CA7_DW1_MASK   0xFFFFFFFF                // RXV_CA7_DW1[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA7_DW1_RXV_CA7_DW1_SHFT   0

/* =====================================================================================

  ---M2M_RXV_CA8_DW0 (0x83000000 + 0x2340)---

    RXV_CA8_DW0[31..0]           - (RW) The value of RXV CA8 DW0 when RXV_LQ_SNR_CTRL is 1.

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA8_DW0_RXV_CA8_DW0_ADDR   WF_M2M_PHY_TOP_11AX_M2M_RXV_CA8_DW0_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA8_DW0_RXV_CA8_DW0_MASK   0xFFFFFFFF                // RXV_CA8_DW0[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA8_DW0_RXV_CA8_DW0_SHFT   0

/* =====================================================================================

  ---M2M_RXV_CA8_DW1 (0x83000000 + 0x2344)---

    RXV_CA8_DW1[31..0]           - (RW) The value of RXV CA8 DW1 when RXV_LQ_SNR_CTRL is 1.

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA8_DW1_RXV_CA8_DW1_ADDR   WF_M2M_PHY_TOP_11AX_M2M_RXV_CA8_DW1_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA8_DW1_RXV_CA8_DW1_MASK   0xFFFFFFFF                // RXV_CA8_DW1[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA8_DW1_RXV_CA8_DW1_SHFT   0

/* =====================================================================================

  ---M2M_RXV_CA9_DW0 (0x83000000 + 0x2348)---

    RXV_CA9_DW0[31..0]           - (RW) The value of RXV CA9 DW0 when RXV_LQ_SNR_CTRL is 1.

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA9_DW0_RXV_CA9_DW0_ADDR   WF_M2M_PHY_TOP_11AX_M2M_RXV_CA9_DW0_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA9_DW0_RXV_CA9_DW0_MASK   0xFFFFFFFF                // RXV_CA9_DW0[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA9_DW0_RXV_CA9_DW0_SHFT   0

/* =====================================================================================

  ---M2M_RXV_CA9_DW1 (0x83000000 + 0x234C)---

    RXV_CA9_DW1[31..0]           - (RW) The value of RXV CA9 DW1 when RXV_LQ_SNR_CTRL is 1.

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA9_DW1_RXV_CA9_DW1_ADDR   WF_M2M_PHY_TOP_11AX_M2M_RXV_CA9_DW1_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA9_DW1_RXV_CA9_DW1_MASK   0xFFFFFFFF                // RXV_CA9_DW1[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RXV_CA9_DW1_RXV_CA9_DW1_SHFT   0

/* =====================================================================================

  ---M2M_RX_TRIG_CFG_DW0 (0x83000000 + 0x2500)---

    RX_TRIG_CFG_DW0[31..0]       - (RO) The value of RX tirg config DW0

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RX_TRIG_CFG_DW0_RX_TRIG_CFG_DW0_ADDR WF_M2M_PHY_TOP_11AX_M2M_RX_TRIG_CFG_DW0_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RX_TRIG_CFG_DW0_RX_TRIG_CFG_DW0_MASK 0xFFFFFFFF                // RX_TRIG_CFG_DW0[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RX_TRIG_CFG_DW0_RX_TRIG_CFG_DW0_SHFT 0

/* =====================================================================================

  ---M2M_RX_TRIG_CFG_DW1 (0x83000000 + 0x2504)---

    RX_TRIG_CFG_DW1[31..0]       - (RO) The value of RX tirg config DW1

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RX_TRIG_CFG_DW1_RX_TRIG_CFG_DW1_ADDR WF_M2M_PHY_TOP_11AX_M2M_RX_TRIG_CFG_DW1_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RX_TRIG_CFG_DW1_RX_TRIG_CFG_DW1_MASK 0xFFFFFFFF                // RX_TRIG_CFG_DW1[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RX_TRIG_CFG_DW1_RX_TRIG_CFG_DW1_SHFT 0

/* =====================================================================================

  ---M2M_RX_TRIG_COM_DW0 (0x83000000 + 0x2508)---

    RX_TRIG_COM_DW0[31..0]       - (RO) The value of RX tirg common DW0

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RX_TRIG_COM_DW0_RX_TRIG_COM_DW0_ADDR WF_M2M_PHY_TOP_11AX_M2M_RX_TRIG_COM_DW0_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RX_TRIG_COM_DW0_RX_TRIG_COM_DW0_MASK 0xFFFFFFFF                // RX_TRIG_COM_DW0[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RX_TRIG_COM_DW0_RX_TRIG_COM_DW0_SHFT 0

/* =====================================================================================

  ---M2M_RX_TRIG_COM_DW1 (0x83000000 + 0x250C)---

    RX_TRIG_COM_DW1[31..0]       - (RO) The value of RX tirg common DW1

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RX_TRIG_COM_DW1_RX_TRIG_COM_DW1_ADDR WF_M2M_PHY_TOP_11AX_M2M_RX_TRIG_COM_DW1_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RX_TRIG_COM_DW1_RX_TRIG_COM_DW1_MASK 0xFFFFFFFF                // RX_TRIG_COM_DW1[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RX_TRIG_COM_DW1_RX_TRIG_COM_DW1_SHFT 0

/* =====================================================================================

  ---M2M_RX_TRIG_DDW0_DW0 (0x83000000 + 0x2510)---

    RX_TRIG_DDW0_DW0[31..0]      - (RO) The value of RX tirg DDW0's DW0

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RX_TRIG_DDW0_DW0_RX_TRIG_DDW0_DW0_ADDR WF_M2M_PHY_TOP_11AX_M2M_RX_TRIG_DDW0_DW0_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RX_TRIG_DDW0_DW0_RX_TRIG_DDW0_DW0_MASK 0xFFFFFFFF                // RX_TRIG_DDW0_DW0[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RX_TRIG_DDW0_DW0_RX_TRIG_DDW0_DW0_SHFT 0

/* =====================================================================================

  ---M2M_RX_TRIG_DDW0_DW1 (0x83000000 + 0x2514)---

    RX_TRIG_DDW0_DW1[31..0]      - (RO) The value of RX tirg DDW0's DW1

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RX_TRIG_DDW0_DW1_RX_TRIG_DDW0_DW1_ADDR WF_M2M_PHY_TOP_11AX_M2M_RX_TRIG_DDW0_DW1_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RX_TRIG_DDW0_DW1_RX_TRIG_DDW0_DW1_MASK 0xFFFFFFFF                // RX_TRIG_DDW0_DW1[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RX_TRIG_DDW0_DW1_RX_TRIG_DDW0_DW1_SHFT 0

/* =====================================================================================

  ---M2M_RX_TRIG_DDW1_DW0 (0x83000000 + 0x2518)---

    RX_TRIG_DDW1_DW0[31..0]      - (RO) The value of RX tirg DDW1's DW0

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RX_TRIG_DDW1_DW0_RX_TRIG_DDW1_DW0_ADDR WF_M2M_PHY_TOP_11AX_M2M_RX_TRIG_DDW1_DW0_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RX_TRIG_DDW1_DW0_RX_TRIG_DDW1_DW0_MASK 0xFFFFFFFF                // RX_TRIG_DDW1_DW0[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RX_TRIG_DDW1_DW0_RX_TRIG_DDW1_DW0_SHFT 0

/* =====================================================================================

  ---M2M_RX_TRIG_DDW1_DW1 (0x83000000 + 0x251C)---

    RX_TRIG_DDW1_DW1[31..0]      - (RO) The value of RX tirg DDW1's DW1

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_RX_TRIG_DDW1_DW1_RX_TRIG_DDW1_DW1_ADDR WF_M2M_PHY_TOP_11AX_M2M_RX_TRIG_DDW1_DW1_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_RX_TRIG_DDW1_DW1_RX_TRIG_DDW1_DW1_MASK 0xFFFFFFFF                // RX_TRIG_DDW1_DW1[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_RX_TRIG_DDW1_DW1_RX_TRIG_DDW1_DW1_SHFT 0

/* =====================================================================================

  ---M2M_MAC_PHY_INTF_CTRL (0x83000000 + 0x3000)---

    U0_RX_DW_CTRL[2..0]          - (RW) 3'h1 : PHY model transfer 1 DW to RMAC per cycle.
                                     3'h2 : PHY model transfer 2 DW to RMAC per cycle.
                                     3'h4 : PHY model transfer 4 DW to RMAC per cycle.
                                     Other value are invalid.
    MAC_PHY_INTF_CTRL_RSV[31..3] - (RW) Reserved

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_MAC_PHY_INTF_CTRL_MAC_PHY_INTF_CTRL_RSV_ADDR WF_M2M_PHY_TOP_11AX_M2M_MAC_PHY_INTF_CTRL_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_MAC_PHY_INTF_CTRL_MAC_PHY_INTF_CTRL_RSV_MASK 0xFFFFFFF8                // MAC_PHY_INTF_CTRL_RSV[31..3]
#define WF_M2M_PHY_TOP_11AX_M2M_MAC_PHY_INTF_CTRL_MAC_PHY_INTF_CTRL_RSV_SHFT 3
#define WF_M2M_PHY_TOP_11AX_M2M_MAC_PHY_INTF_CTRL_U0_RX_DW_CTRL_ADDR WF_M2M_PHY_TOP_11AX_M2M_MAC_PHY_INTF_CTRL_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_MAC_PHY_INTF_CTRL_U0_RX_DW_CTRL_MASK 0x00000007                // U0_RX_DW_CTRL[2..0]
#define WF_M2M_PHY_TOP_11AX_M2M_MAC_PHY_INTF_CTRL_U0_RX_DW_CTRL_SHFT 0

/* =====================================================================================

  ---M2M_CHN_CTRL (0x83000000 + 0x3010)---

    CHN_CTRL_ENABLE[0]           - (RW) 1: Enable channle model control. Only enable this bit at AP side.
                                     0: Disable channel model control.
    CHN_CTRL_RSV[31..1]          - (RW) Reserved

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_CTRL_CHN_CTRL_RSV_ADDR     WF_M2M_PHY_TOP_11AX_M2M_CHN_CTRL_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_CTRL_CHN_CTRL_RSV_MASK     0xFFFFFFFE                // CHN_CTRL_RSV[31..1]
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_CTRL_CHN_CTRL_RSV_SHFT     1
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_CTRL_CHN_CTRL_ENABLE_ADDR  WF_M2M_PHY_TOP_11AX_M2M_CHN_CTRL_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_CTRL_CHN_CTRL_ENABLE_MASK  0x00000001                // CHN_CTRL_ENABLE[0]
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_CTRL_CHN_CTRL_ENABLE_SHFT  0

/* =====================================================================================

  ---M2M_CHN_BER (0x83000000 + 0x3014)---

    CHN_BER_DW_CNT[15..0]        - (RW) DW number to be destroyed by channel model.
    CHN_BER_RSV[31..16]          - (RW) Reserved

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_BER_CHN_BER_RSV_ADDR       WF_M2M_PHY_TOP_11AX_M2M_CHN_BER_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_BER_CHN_BER_RSV_MASK       0xFFFF0000                // CHN_BER_RSV[31..16]
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_BER_CHN_BER_RSV_SHFT       16
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_BER_CHN_BER_DW_CNT_ADDR    WF_M2M_PHY_TOP_11AX_M2M_CHN_BER_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_BER_CHN_BER_DW_CNT_MASK    0x0000FFFF                // CHN_BER_DW_CNT[15..0]
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_BER_CHN_BER_DW_CNT_SHFT    0

/* =====================================================================================

  ---M2M_CHN_TICK_CTRL_0 (0x83000000 + 0x3018)---

    CHN_TICK_CNT_MAX[11..0]      - (RW) Max US count for system tick timer. When system tick timer reaches this value, it will be reset to 0.
    CHN_TICK_CTRL_0_RSV[31..12]  - (RW) Reserved

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_TICK_CTRL_0_CHN_TICK_CTRL_0_RSV_ADDR WF_M2M_PHY_TOP_11AX_M2M_CHN_TICK_CTRL_0_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_TICK_CTRL_0_CHN_TICK_CTRL_0_RSV_MASK 0xFFFFF000                // CHN_TICK_CTRL_0_RSV[31..12]
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_TICK_CTRL_0_CHN_TICK_CTRL_0_RSV_SHFT 12
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_TICK_CTRL_0_CHN_TICK_CNT_MAX_ADDR WF_M2M_PHY_TOP_11AX_M2M_CHN_TICK_CTRL_0_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_TICK_CTRL_0_CHN_TICK_CNT_MAX_MASK 0x00000FFF                // CHN_TICK_CNT_MAX[11..0]
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_TICK_CTRL_0_CHN_TICK_CNT_MAX_SHFT 0

/* =====================================================================================

  ---M2M_CHN_TICK_CTRL_1 (0x83000000 + 0x301C)---

    CHN_SYS_TIME_MAX[31..0]      - (RW) MAX value for system timer. When system timer reaches this value, it will be reset to 0.

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_TICK_CTRL_1_CHN_SYS_TIME_MAX_ADDR WF_M2M_PHY_TOP_11AX_M2M_CHN_TICK_CTRL_1_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_TICK_CTRL_1_CHN_SYS_TIME_MAX_MASK 0xFFFFFFFF                // CHN_SYS_TIME_MAX[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_TICK_CTRL_1_CHN_SYS_TIME_MAX_SHFT 0

/* =====================================================================================

  ---M2M_CHN_U0_TX_ERR (0x83000000 + 0x3020)---

    CHN_U0_TX_TOO_LATE_CNT[15..0] - (RO) Number count that Channel model can't provide data on time.
    CHN_U0_TX_TOO_LATE_RATE[23..16] - (RO) TX rate when Channel model can't provide data on time.
    CHN_U0_TX_TOO_LATE_PFD[27..24] - (RO) TX PFD when Channel model can't provide data on time.
    CHN_U0_TX_TOO_LATE_BW[30..28] - (RO) TX BW when Channel model can't provide data on time.
    CHN_U0_TX_TOO_LATE[31]       - (RO) When this bit is set to 1, it means Channel model can't provide data on time.

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U0_TX_ERR_CHN_U0_TX_TOO_LATE_ADDR WF_M2M_PHY_TOP_11AX_M2M_CHN_U0_TX_ERR_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U0_TX_ERR_CHN_U0_TX_TOO_LATE_MASK 0x80000000                // CHN_U0_TX_TOO_LATE[31]
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U0_TX_ERR_CHN_U0_TX_TOO_LATE_SHFT 31
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U0_TX_ERR_CHN_U0_TX_TOO_LATE_BW_ADDR WF_M2M_PHY_TOP_11AX_M2M_CHN_U0_TX_ERR_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U0_TX_ERR_CHN_U0_TX_TOO_LATE_BW_MASK 0x70000000                // CHN_U0_TX_TOO_LATE_BW[30..28]
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U0_TX_ERR_CHN_U0_TX_TOO_LATE_BW_SHFT 28
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U0_TX_ERR_CHN_U0_TX_TOO_LATE_PFD_ADDR WF_M2M_PHY_TOP_11AX_M2M_CHN_U0_TX_ERR_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U0_TX_ERR_CHN_U0_TX_TOO_LATE_PFD_MASK 0x0F000000                // CHN_U0_TX_TOO_LATE_PFD[27..24]
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U0_TX_ERR_CHN_U0_TX_TOO_LATE_PFD_SHFT 24
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U0_TX_ERR_CHN_U0_TX_TOO_LATE_RATE_ADDR WF_M2M_PHY_TOP_11AX_M2M_CHN_U0_TX_ERR_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U0_TX_ERR_CHN_U0_TX_TOO_LATE_RATE_MASK 0x00FF0000                // CHN_U0_TX_TOO_LATE_RATE[23..16]
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U0_TX_ERR_CHN_U0_TX_TOO_LATE_RATE_SHFT 16
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U0_TX_ERR_CHN_U0_TX_TOO_LATE_CNT_ADDR WF_M2M_PHY_TOP_11AX_M2M_CHN_U0_TX_ERR_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U0_TX_ERR_CHN_U0_TX_TOO_LATE_CNT_MASK 0x0000FFFF                // CHN_U0_TX_TOO_LATE_CNT[15..0]
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U0_TX_ERR_CHN_U0_TX_TOO_LATE_CNT_SHFT 0

/* =====================================================================================

  ---M2M_CHN_U1_TX_ERR (0x83000000 + 0x3024)---

    CHN_U1_TX_TOO_LATE_CNT[15..0] - (RO) Number count that Channel model can't provide data on time.
    CHN_U1_TX_TOO_LATE_RATE[23..16] - (RO) TX rate when Channel model can't provide data on time.
    CHN_U1_TX_TOO_LATE_PFD[27..24] - (RO) TX PFD when Channel model can't provide data on time.
    CHN_U1_TX_TOO_LATE_BW[30..28] - (RO) TX BW when Channel model can't provide data on time.
    CHN_U1_TX_TOO_LATE[31]       - (RO) When this bit is set to 1, it means Channel model can't provide data on time.

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U1_TX_ERR_CHN_U1_TX_TOO_LATE_ADDR WF_M2M_PHY_TOP_11AX_M2M_CHN_U1_TX_ERR_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U1_TX_ERR_CHN_U1_TX_TOO_LATE_MASK 0x80000000                // CHN_U1_TX_TOO_LATE[31]
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U1_TX_ERR_CHN_U1_TX_TOO_LATE_SHFT 31
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U1_TX_ERR_CHN_U1_TX_TOO_LATE_BW_ADDR WF_M2M_PHY_TOP_11AX_M2M_CHN_U1_TX_ERR_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U1_TX_ERR_CHN_U1_TX_TOO_LATE_BW_MASK 0x70000000                // CHN_U1_TX_TOO_LATE_BW[30..28]
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U1_TX_ERR_CHN_U1_TX_TOO_LATE_BW_SHFT 28
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U1_TX_ERR_CHN_U1_TX_TOO_LATE_PFD_ADDR WF_M2M_PHY_TOP_11AX_M2M_CHN_U1_TX_ERR_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U1_TX_ERR_CHN_U1_TX_TOO_LATE_PFD_MASK 0x0F000000                // CHN_U1_TX_TOO_LATE_PFD[27..24]
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U1_TX_ERR_CHN_U1_TX_TOO_LATE_PFD_SHFT 24
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U1_TX_ERR_CHN_U1_TX_TOO_LATE_RATE_ADDR WF_M2M_PHY_TOP_11AX_M2M_CHN_U1_TX_ERR_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U1_TX_ERR_CHN_U1_TX_TOO_LATE_RATE_MASK 0x00FF0000                // CHN_U1_TX_TOO_LATE_RATE[23..16]
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U1_TX_ERR_CHN_U1_TX_TOO_LATE_RATE_SHFT 16
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U1_TX_ERR_CHN_U1_TX_TOO_LATE_CNT_ADDR WF_M2M_PHY_TOP_11AX_M2M_CHN_U1_TX_ERR_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U1_TX_ERR_CHN_U1_TX_TOO_LATE_CNT_MASK 0x0000FFFF                // CHN_U1_TX_TOO_LATE_CNT[15..0]
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U1_TX_ERR_CHN_U1_TX_TOO_LATE_CNT_SHFT 0

/* =====================================================================================

  ---M2M_CHN_U2_TX_ERR (0x83000000 + 0x3028)---

    CHN_U2_TX_TOO_LATE_CNT[15..0] - (RO) Number count that Channel model can't provide data on time.
    CHN_U2_TX_TOO_LATE_RATE[23..16] - (RO) TX rate when Channel model can't provide data on time.
    CHN_U2_TX_TOO_LATE_PFD[27..24] - (RO) TX PFD when Channel model can't provide data on time.
    CHN_U2_TX_TOO_LATE_BW[30..28] - (RO) TX BW when Channel model can't provide data on time.
    CHN_U2_TX_TOO_LATE[31]       - (RO) When this bit is set to 1, it means Channel model can't provide data on time.

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U2_TX_ERR_CHN_U2_TX_TOO_LATE_ADDR WF_M2M_PHY_TOP_11AX_M2M_CHN_U2_TX_ERR_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U2_TX_ERR_CHN_U2_TX_TOO_LATE_MASK 0x80000000                // CHN_U2_TX_TOO_LATE[31]
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U2_TX_ERR_CHN_U2_TX_TOO_LATE_SHFT 31
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U2_TX_ERR_CHN_U2_TX_TOO_LATE_BW_ADDR WF_M2M_PHY_TOP_11AX_M2M_CHN_U2_TX_ERR_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U2_TX_ERR_CHN_U2_TX_TOO_LATE_BW_MASK 0x70000000                // CHN_U2_TX_TOO_LATE_BW[30..28]
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U2_TX_ERR_CHN_U2_TX_TOO_LATE_BW_SHFT 28
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U2_TX_ERR_CHN_U2_TX_TOO_LATE_PFD_ADDR WF_M2M_PHY_TOP_11AX_M2M_CHN_U2_TX_ERR_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U2_TX_ERR_CHN_U2_TX_TOO_LATE_PFD_MASK 0x0F000000                // CHN_U2_TX_TOO_LATE_PFD[27..24]
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U2_TX_ERR_CHN_U2_TX_TOO_LATE_PFD_SHFT 24
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U2_TX_ERR_CHN_U2_TX_TOO_LATE_RATE_ADDR WF_M2M_PHY_TOP_11AX_M2M_CHN_U2_TX_ERR_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U2_TX_ERR_CHN_U2_TX_TOO_LATE_RATE_MASK 0x00FF0000                // CHN_U2_TX_TOO_LATE_RATE[23..16]
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U2_TX_ERR_CHN_U2_TX_TOO_LATE_RATE_SHFT 16
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U2_TX_ERR_CHN_U2_TX_TOO_LATE_CNT_ADDR WF_M2M_PHY_TOP_11AX_M2M_CHN_U2_TX_ERR_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U2_TX_ERR_CHN_U2_TX_TOO_LATE_CNT_MASK 0x0000FFFF                // CHN_U2_TX_TOO_LATE_CNT[15..0]
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U2_TX_ERR_CHN_U2_TX_TOO_LATE_CNT_SHFT 0

/* =====================================================================================

  ---M2M_CHN_U3_TX_ERR (0x83000000 + 0x302c)---

    CHN_U3_TX_TOO_LATE_CNT[15..0] - (RO) Number count that Channel model can't provide data on time.
    CHN_U3_TX_TOO_LATE_RATE[23..16] - (RO) TX rate when Channel model can't provide data on time.
    CHN_U3_TX_TOO_LATE_PFD[27..24] - (RO) TX PFD when Channel model can't provide data on time.
    CHN_U3_TX_TOO_LATE_BW[30..28] - (RO) TX BW when Channel model can't provide data on time.
    CHN_U3_TX_TOO_LATE[31]       - (RO) When this bit is set to 1, it means Channel model can't provide data on time.

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U3_TX_ERR_CHN_U3_TX_TOO_LATE_ADDR WF_M2M_PHY_TOP_11AX_M2M_CHN_U3_TX_ERR_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U3_TX_ERR_CHN_U3_TX_TOO_LATE_MASK 0x80000000                // CHN_U3_TX_TOO_LATE[31]
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U3_TX_ERR_CHN_U3_TX_TOO_LATE_SHFT 31
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U3_TX_ERR_CHN_U3_TX_TOO_LATE_BW_ADDR WF_M2M_PHY_TOP_11AX_M2M_CHN_U3_TX_ERR_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U3_TX_ERR_CHN_U3_TX_TOO_LATE_BW_MASK 0x70000000                // CHN_U3_TX_TOO_LATE_BW[30..28]
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U3_TX_ERR_CHN_U3_TX_TOO_LATE_BW_SHFT 28
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U3_TX_ERR_CHN_U3_TX_TOO_LATE_PFD_ADDR WF_M2M_PHY_TOP_11AX_M2M_CHN_U3_TX_ERR_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U3_TX_ERR_CHN_U3_TX_TOO_LATE_PFD_MASK 0x0F000000                // CHN_U3_TX_TOO_LATE_PFD[27..24]
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U3_TX_ERR_CHN_U3_TX_TOO_LATE_PFD_SHFT 24
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U3_TX_ERR_CHN_U3_TX_TOO_LATE_RATE_ADDR WF_M2M_PHY_TOP_11AX_M2M_CHN_U3_TX_ERR_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U3_TX_ERR_CHN_U3_TX_TOO_LATE_RATE_MASK 0x00FF0000                // CHN_U3_TX_TOO_LATE_RATE[23..16]
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U3_TX_ERR_CHN_U3_TX_TOO_LATE_RATE_SHFT 16
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U3_TX_ERR_CHN_U3_TX_TOO_LATE_CNT_ADDR WF_M2M_PHY_TOP_11AX_M2M_CHN_U3_TX_ERR_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U3_TX_ERR_CHN_U3_TX_TOO_LATE_CNT_MASK 0x0000FFFF                // CHN_U3_TX_TOO_LATE_CNT[15..0]
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U3_TX_ERR_CHN_U3_TX_TOO_LATE_CNT_SHFT 0

/* =====================================================================================

  ---M2M_CHN_U0_RX_ERR (0x83000000 + 0x3040)---

    CHN_U0_RX_TOO_LATE_CNT[15..0] - (RO) Number count that Channel model can't provide data on time.
    CHN_U0_RX_TOO_LATE_RATE[23..16] - (RO) RX rate when Channel model can't provide data on time.
    CHN_U0_RX_TOO_LATE_PFD[27..24] - (RO) RX PFD when Channel model can't provide data on time.
    CHN_U0_RX_TOO_LATE_BW[30..28] - (RO) RX BW when Channel model can't provide data on time.
    CHN_U0_RX_TOO_LATE[31]       - (RO) When this bit is set to 1, it means Channel model can't provide data on time.

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U0_RX_ERR_CHN_U0_RX_TOO_LATE_ADDR WF_M2M_PHY_TOP_11AX_M2M_CHN_U0_RX_ERR_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U0_RX_ERR_CHN_U0_RX_TOO_LATE_MASK 0x80000000                // CHN_U0_RX_TOO_LATE[31]
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U0_RX_ERR_CHN_U0_RX_TOO_LATE_SHFT 31
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U0_RX_ERR_CHN_U0_RX_TOO_LATE_BW_ADDR WF_M2M_PHY_TOP_11AX_M2M_CHN_U0_RX_ERR_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U0_RX_ERR_CHN_U0_RX_TOO_LATE_BW_MASK 0x70000000                // CHN_U0_RX_TOO_LATE_BW[30..28]
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U0_RX_ERR_CHN_U0_RX_TOO_LATE_BW_SHFT 28
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U0_RX_ERR_CHN_U0_RX_TOO_LATE_PFD_ADDR WF_M2M_PHY_TOP_11AX_M2M_CHN_U0_RX_ERR_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U0_RX_ERR_CHN_U0_RX_TOO_LATE_PFD_MASK 0x0F000000                // CHN_U0_RX_TOO_LATE_PFD[27..24]
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U0_RX_ERR_CHN_U0_RX_TOO_LATE_PFD_SHFT 24
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U0_RX_ERR_CHN_U0_RX_TOO_LATE_RATE_ADDR WF_M2M_PHY_TOP_11AX_M2M_CHN_U0_RX_ERR_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U0_RX_ERR_CHN_U0_RX_TOO_LATE_RATE_MASK 0x00FF0000                // CHN_U0_RX_TOO_LATE_RATE[23..16]
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U0_RX_ERR_CHN_U0_RX_TOO_LATE_RATE_SHFT 16
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U0_RX_ERR_CHN_U0_RX_TOO_LATE_CNT_ADDR WF_M2M_PHY_TOP_11AX_M2M_CHN_U0_RX_ERR_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U0_RX_ERR_CHN_U0_RX_TOO_LATE_CNT_MASK 0x0000FFFF                // CHN_U0_RX_TOO_LATE_CNT[15..0]
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U0_RX_ERR_CHN_U0_RX_TOO_LATE_CNT_SHFT 0

/* =====================================================================================

  ---M2M_CHN_U1_RX_ERR (0x83000000 + 0x3044)---

    CHN_U1_RX_TOO_LATE_CNT[15..0] - (RO) Number count that Channel model can't provide data on time.
    CHN_U1_RX_TOO_LATE_RATE[23..16] - (RO) RX rate when Channel model can't provide data on time.
    CHN_U1_RX_TOO_LATE_PFD[27..24] - (RO) RX PFD when Channel model can't provide data on time.
    CHN_U1_RX_TOO_LATE_BW[30..28] - (RO) RX BW when Channel model can't provide data on time.
    CHN_U1_RX_TOO_LATE[31]       - (RO) When this bit is set to 1, it means Channel model can't provide data on time.

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U1_RX_ERR_CHN_U1_RX_TOO_LATE_ADDR WF_M2M_PHY_TOP_11AX_M2M_CHN_U1_RX_ERR_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U1_RX_ERR_CHN_U1_RX_TOO_LATE_MASK 0x80000000                // CHN_U1_RX_TOO_LATE[31]
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U1_RX_ERR_CHN_U1_RX_TOO_LATE_SHFT 31
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U1_RX_ERR_CHN_U1_RX_TOO_LATE_BW_ADDR WF_M2M_PHY_TOP_11AX_M2M_CHN_U1_RX_ERR_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U1_RX_ERR_CHN_U1_RX_TOO_LATE_BW_MASK 0x70000000                // CHN_U1_RX_TOO_LATE_BW[30..28]
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U1_RX_ERR_CHN_U1_RX_TOO_LATE_BW_SHFT 28
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U1_RX_ERR_CHN_U1_RX_TOO_LATE_PFD_ADDR WF_M2M_PHY_TOP_11AX_M2M_CHN_U1_RX_ERR_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U1_RX_ERR_CHN_U1_RX_TOO_LATE_PFD_MASK 0x0F000000                // CHN_U1_RX_TOO_LATE_PFD[27..24]
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U1_RX_ERR_CHN_U1_RX_TOO_LATE_PFD_SHFT 24
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U1_RX_ERR_CHN_U1_RX_TOO_LATE_RATE_ADDR WF_M2M_PHY_TOP_11AX_M2M_CHN_U1_RX_ERR_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U1_RX_ERR_CHN_U1_RX_TOO_LATE_RATE_MASK 0x00FF0000                // CHN_U1_RX_TOO_LATE_RATE[23..16]
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U1_RX_ERR_CHN_U1_RX_TOO_LATE_RATE_SHFT 16
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U1_RX_ERR_CHN_U1_RX_TOO_LATE_CNT_ADDR WF_M2M_PHY_TOP_11AX_M2M_CHN_U1_RX_ERR_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U1_RX_ERR_CHN_U1_RX_TOO_LATE_CNT_MASK 0x0000FFFF                // CHN_U1_RX_TOO_LATE_CNT[15..0]
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U1_RX_ERR_CHN_U1_RX_TOO_LATE_CNT_SHFT 0

/* =====================================================================================

  ---M2M_CHN_U2_RX_ERR (0x83000000 + 0x3048)---

    CHN_U2_RX_TOO_LATE_CNT[15..0] - (RO) Number count that Channel model can't provide data on time.
    CHN_U2_RX_TOO_LATE_RATE[23..16] - (RO) RX rate when Channel model can't provide data on time.
    CHN_U2_RX_TOO_LATE_PFD[27..24] - (RO) RX PFD when Channel model can't provide data on time.
    CHN_U2_RX_TOO_LATE_BW[30..28] - (RO) RX BW when Channel model can't provide data on time.
    CHN_U2_RX_TOO_LATE[31]       - (RO) When this bit is set to 1, it means Channel model can't provide data on time.

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U2_RX_ERR_CHN_U2_RX_TOO_LATE_ADDR WF_M2M_PHY_TOP_11AX_M2M_CHN_U2_RX_ERR_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U2_RX_ERR_CHN_U2_RX_TOO_LATE_MASK 0x80000000                // CHN_U2_RX_TOO_LATE[31]
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U2_RX_ERR_CHN_U2_RX_TOO_LATE_SHFT 31
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U2_RX_ERR_CHN_U2_RX_TOO_LATE_BW_ADDR WF_M2M_PHY_TOP_11AX_M2M_CHN_U2_RX_ERR_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U2_RX_ERR_CHN_U2_RX_TOO_LATE_BW_MASK 0x70000000                // CHN_U2_RX_TOO_LATE_BW[30..28]
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U2_RX_ERR_CHN_U2_RX_TOO_LATE_BW_SHFT 28
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U2_RX_ERR_CHN_U2_RX_TOO_LATE_PFD_ADDR WF_M2M_PHY_TOP_11AX_M2M_CHN_U2_RX_ERR_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U2_RX_ERR_CHN_U2_RX_TOO_LATE_PFD_MASK 0x0F000000                // CHN_U2_RX_TOO_LATE_PFD[27..24]
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U2_RX_ERR_CHN_U2_RX_TOO_LATE_PFD_SHFT 24
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U2_RX_ERR_CHN_U2_RX_TOO_LATE_RATE_ADDR WF_M2M_PHY_TOP_11AX_M2M_CHN_U2_RX_ERR_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U2_RX_ERR_CHN_U2_RX_TOO_LATE_RATE_MASK 0x00FF0000                // CHN_U2_RX_TOO_LATE_RATE[23..16]
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U2_RX_ERR_CHN_U2_RX_TOO_LATE_RATE_SHFT 16
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U2_RX_ERR_CHN_U2_RX_TOO_LATE_CNT_ADDR WF_M2M_PHY_TOP_11AX_M2M_CHN_U2_RX_ERR_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U2_RX_ERR_CHN_U2_RX_TOO_LATE_CNT_MASK 0x0000FFFF                // CHN_U2_RX_TOO_LATE_CNT[15..0]
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U2_RX_ERR_CHN_U2_RX_TOO_LATE_CNT_SHFT 0

/* =====================================================================================

  ---M2M_CHN_U3_RX_ERR (0x83000000 + 0x304c)---

    CHN_U3_RX_TOO_LATE_CNT[15..0] - (RO) Number count that Channel model can't provide data on time.
    CHN_U3_RX_TOO_LATE_RATE[23..16] - (RO) RX rate when Channel model can't provide data on time.
    CHN_U3_RX_TOO_LATE_PFD[27..24] - (RO) RX PFD when Channel model can't provide data on time.
    CHN_U3_RX_TOO_LATE_BW[30..28] - (RO) RX BW when Channel model can't provide data on time.
    CHN_U3_RX_TOO_LATE[31]       - (RO) When this bit is set to 1, it means Channel model can't provide data on time.

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U3_RX_ERR_CHN_U3_RX_TOO_LATE_ADDR WF_M2M_PHY_TOP_11AX_M2M_CHN_U3_RX_ERR_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U3_RX_ERR_CHN_U3_RX_TOO_LATE_MASK 0x80000000                // CHN_U3_RX_TOO_LATE[31]
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U3_RX_ERR_CHN_U3_RX_TOO_LATE_SHFT 31
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U3_RX_ERR_CHN_U3_RX_TOO_LATE_BW_ADDR WF_M2M_PHY_TOP_11AX_M2M_CHN_U3_RX_ERR_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U3_RX_ERR_CHN_U3_RX_TOO_LATE_BW_MASK 0x70000000                // CHN_U3_RX_TOO_LATE_BW[30..28]
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U3_RX_ERR_CHN_U3_RX_TOO_LATE_BW_SHFT 28
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U3_RX_ERR_CHN_U3_RX_TOO_LATE_PFD_ADDR WF_M2M_PHY_TOP_11AX_M2M_CHN_U3_RX_ERR_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U3_RX_ERR_CHN_U3_RX_TOO_LATE_PFD_MASK 0x0F000000                // CHN_U3_RX_TOO_LATE_PFD[27..24]
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U3_RX_ERR_CHN_U3_RX_TOO_LATE_PFD_SHFT 24
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U3_RX_ERR_CHN_U3_RX_TOO_LATE_RATE_ADDR WF_M2M_PHY_TOP_11AX_M2M_CHN_U3_RX_ERR_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U3_RX_ERR_CHN_U3_RX_TOO_LATE_RATE_MASK 0x00FF0000                // CHN_U3_RX_TOO_LATE_RATE[23..16]
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U3_RX_ERR_CHN_U3_RX_TOO_LATE_RATE_SHFT 16
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U3_RX_ERR_CHN_U3_RX_TOO_LATE_CNT_ADDR WF_M2M_PHY_TOP_11AX_M2M_CHN_U3_RX_ERR_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U3_RX_ERR_CHN_U3_RX_TOO_LATE_CNT_MASK 0x0000FFFF                // CHN_U3_RX_TOO_LATE_CNT[15..0]
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U3_RX_ERR_CHN_U3_RX_TOO_LATE_CNT_SHFT 0

/* =====================================================================================

  ---M2M_CHN_U0_BER_VALUE (0x83000000 + 0x3060)---

    CHN_U0_BER_VALUE[31..0]      - (RO) U0 BER value from channel model

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U0_BER_VALUE_CHN_U0_BER_VALUE_ADDR WF_M2M_PHY_TOP_11AX_M2M_CHN_U0_BER_VALUE_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U0_BER_VALUE_CHN_U0_BER_VALUE_MASK 0xFFFFFFFF                // CHN_U0_BER_VALUE[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U0_BER_VALUE_CHN_U0_BER_VALUE_SHFT 0

/* =====================================================================================

  ---M2M_CHN_U0_TX_BER_0 (0x83000000 + 0x3080)---

    CHN_U0_TX_BER_0[31..0]       - (RO) Total request count of BER for U0 TX

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U0_TX_BER_0_CHN_U0_TX_BER_0_ADDR WF_M2M_PHY_TOP_11AX_M2M_CHN_U0_TX_BER_0_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U0_TX_BER_0_CHN_U0_TX_BER_0_MASK 0xFFFFFFFF                // CHN_U0_TX_BER_0[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U0_TX_BER_0_CHN_U0_TX_BER_0_SHFT 0

/* =====================================================================================

  ---M2M_CHN_U0_TX_BER_1 (0x83000000 + 0x3084)---

    CHN_U0_TX_BER_1[31..0]       - (RO) Total count to make a decision to destroy data based on the comparison of a random value and BER value for U0 TX.

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U0_TX_BER_1_CHN_U0_TX_BER_1_ADDR WF_M2M_PHY_TOP_11AX_M2M_CHN_U0_TX_BER_1_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U0_TX_BER_1_CHN_U0_TX_BER_1_MASK 0xFFFFFFFF                // CHN_U0_TX_BER_1[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U0_TX_BER_1_CHN_U0_TX_BER_1_SHFT 0

/* =====================================================================================

  ---M2M_CHN_U0_RX_BER_0 (0x83000000 + 0x30a0)---

    CHN_U0_RX_BER_0[31..0]       - (RO) Total request count of BER for U0 RX

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U0_RX_BER_0_CHN_U0_RX_BER_0_ADDR WF_M2M_PHY_TOP_11AX_M2M_CHN_U0_RX_BER_0_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U0_RX_BER_0_CHN_U0_RX_BER_0_MASK 0xFFFFFFFF                // CHN_U0_RX_BER_0[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U0_RX_BER_0_CHN_U0_RX_BER_0_SHFT 0

/* =====================================================================================

  ---M2M_CHN_U0_RX_BER_1 (0x83000000 + 0x30a4)---

    CHN_U0_RX_BER_1[31..0]       - (RO) Total count to make a decision to destroy data based on the comparison of a random value and BER value for U0 RX.

 =====================================================================================*/
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U0_RX_BER_1_CHN_U0_RX_BER_1_ADDR WF_M2M_PHY_TOP_11AX_M2M_CHN_U0_RX_BER_1_ADDR
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U0_RX_BER_1_CHN_U0_RX_BER_1_MASK 0xFFFFFFFF                // CHN_U0_RX_BER_1[31..0]
#define WF_M2M_PHY_TOP_11AX_M2M_CHN_U0_RX_BER_1_CHN_U0_RX_BER_1_SHFT 0

#ifdef __cplusplus
}
#endif

#endif // __WF_M2M_PHY_TOP_11AX_REGS_H__
